Updated the docs to point to the new verilator top

lowRISC · Feb 29, 2024 · 8264f86 · 8264f86
1 parent e23912c
commit 8264f86
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Showing 3 changed files with 8 additions and 6 deletions.
diff --git a/.gitignore b/.gitignore
@@ -1,4 +1,7 @@
 build/
 .venv/
+__pycache__/
 target/
 *.fst
+*.log
+*.csv
diff --git a/README.md b/README.md
@@ -423,7 +423,7 @@ in `ibex_demo_system.core`
 The Demo System simulator binary can be built via FuseSoC. From the Ibex
 repository root run:
 
-```
+```sh
 fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
 ```
 
@@ -435,14 +435,13 @@ built as described above. Use `./sw/c/build/demo/hello_world/demo` to run the `d
 binary.
 
 Run from the repository root run:
-```
+```sh
 # For example :
-./build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system \
+./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator \
   --meminit=ram,./sw/c/build/demo/hello_world/demo
 
 # You need to substitute the <sw_elf_file> for a binary we have build above.
-./build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system [-t] --meminit=ram,<sw_elf_file>
-
+./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator [-t] --meminit=ram,<sw_elf_file>
 ```
 
 Pass `-t` to get an FST trace of execution that can be viewed with

diff --git a/flake.nix b/flake.nix
@@ -90,7 +90,7 @@
           Build ibex simulation verilator model :
               fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:ibex:demo_system
           Run ibex simulator verilator model :
-              ./build/lowrisc_ibex_demo_system_0/sim-verilator/Vibex_demo_system -t \
+              ./build/lowrisc_ibex_demo_system_0/sim-verilator/Vtop_verilator -t \
                 --meminit=ram,sw/c/build/demo/hello_world/demo
           Build ibex-demo-system FPGA bitstream for Arty-A7 :
               fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system