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Update ISA.yml
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lhtin authored Dec 12, 2023
1 parent 399bf22 commit cbf8df5
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion app/riscv-isa-dev/public/ISA.yml
Original file line number Diff line number Diff line change
Expand Up @@ -409,7 +409,7 @@ RV64I: &id_rv64i
rd_32bit = low_32bit(rs1) + low_32bit(rs2)
rd = sign_extend(rd_32bit)
SUBW:
asm: sll rd, rs1, rs2
asm: subw rd, rs1, rs2
code: |
rd_32bit = low_32bit(rs1) - low_32bit(rs2)
rd = sign_extend(rd_32bit)
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