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Added simple cocotb testbench for CU Cocotb Test #38: Commit 2c9b707 pushed by jxwleong
September 12, 2023 05:40 1m 12s master
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September 12, 2023 05:40 1m 12s
Update .gitignore to ignore output files generated by cocotb Cocotb Test #37: Commit 229fc59 pushed by jxwleong
September 8, 2023 06:39 1m 5s master
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September 8, 2023 06:39 1m 5s
Added cocotb testbench for addSubtractor Cocotb Test #36: Commit b46de55 pushed by jxwleong
September 8, 2023 05:52 51s master
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September 8, 2023 05:52 51s
Added cocotb testbench for DFF_reg Cocotb Test #35: Commit 1ed3cb1 pushed by jxwleong
September 8, 2023 05:35 50s master
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September 8, 2023 05:35 50s
Added cocotb testbench for DFF_reg Verilog Simulation #19: Commit 1ed3cb1 pushed by jxwleong
September 8, 2023 05:35 21s master
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September 8, 2023 05:35 21s
Added cocotb testbench for mux4to1 Cocotb Test #34: Commit 06ea9be pushed by jxwleong
September 8, 2023 04:41 1m 19s master
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September 8, 2023 04:41 1m 19s
Added cocotb testbench for mux4to1 Verilog Simulation #18: Commit 06ea9be pushed by jxwleong
September 8, 2023 04:41 31s master
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September 8, 2023 04:41 31s
Added better naming for test functions Cocotb Test #33: Commit 75e2754 pushed by jxwleong
September 8, 2023 03:28 44s master
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September 8, 2023 03:28 44s
Added better naming for test functions Verilog Simulation #17: Commit 75e2754 pushed by jxwleong
September 8, 2023 03:28 19s master
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September 8, 2023 03:28 19s
Fixed Makefile which causes the build fail due to path changes Verilog Simulation #16: Commit 1e490c3 pushed by jxwleong
September 8, 2023 03:20 23s master
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September 8, 2023 03:20 23s
Fixed Makefile which causes the build fail due to path changes Cocotb Test #32: Commit 1e490c3 pushed by jxwleong
September 8, 2023 03:20 43s master
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September 8, 2023 03:20 43s
Moved cocotb Makefile into testbench/cocotb Cocotb Test #31: Commit 4acd3f1 pushed by jxwleong
September 8, 2023 03:16 29s master
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September 8, 2023 03:16 29s
Moved cocotb Makefile into testbench/cocotb Verilog Simulation #15: Commit 4acd3f1 pushed by jxwleong
September 8, 2023 03:16 24s master
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September 8, 2023 03:16 24s
Added paths-ignore for the github workflow files Cocotb Test #30: Commit da00715 pushed by jxwleong
September 8, 2023 03:15 44s master
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September 8, 2023 03:15 44s
Added paths-ignore for the github workflow files Verilog Simulation #14: Commit da00715 pushed by jxwleong
September 8, 2023 03:15 21s master
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September 8, 2023 03:15 21s
Renamed 'makefile'=>'Makefile' Cocotb Test #29: Commit 3777a13 pushed by jxwleong
September 8, 2023 03:10 41s master
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September 8, 2023 03:10 41s
Renamed 'makefile'=>'Makefile' Verilog Simulation #13: Commit 3777a13 pushed by jxwleong
September 8, 2023 03:10 21s master
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September 8, 2023 03:10 21s
Added some print statements for rtl_tb Cocotb Test #28: Commit ce6e70e pushed by jxwleong
September 7, 2023 11:34 1m 4s master
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September 7, 2023 11:34 1m 4s
Added some print statements for rtl_tb Verilog Simulation #12: Commit ce6e70e pushed by jxwleong
September 7, 2023 11:34 19s master
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September 7, 2023 11:34 19s
Moved unused verilog file to archive Cocotb Test #27: Commit 35789f7 pushed by jxwleong
September 7, 2023 08:29 36s master
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September 7, 2023 08:29 36s
Moved unused verilog file to archive Verilog Simulation #11: Commit 35789f7 pushed by jxwleong
September 7, 2023 08:29 17s master
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September 7, 2023 08:29 17s
Fixed some typo in README Cocotb Test #26: Commit abbd50c pushed by jxwleong
September 7, 2023 08:27 45s master
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September 7, 2023 08:27 45s
Fixed some typo in README Verilog Simulation #10: Commit abbd50c pushed by jxwleong
September 7, 2023 08:27 19s master
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September 7, 2023 08:27 19s
Rename new status badge for Verilog Simulation Verilog Simulation #9: Commit 00c1da3 pushed by jxwleong
September 7, 2023 08:18 17s master
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September 7, 2023 08:18 17s
Rename new status badge for Verilog Simulation Cocotb Test #25: Commit 00c1da3 pushed by jxwleong
September 7, 2023 08:18 41s master
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September 7, 2023 08:18 41s