v0.26: Improved testing of processors

- Performance improvement of the simulation start.
- Improved the gui to modify the k-map layout.
- Improved testing of processors.
- Improved the layout of fsm transitions in the fsm editor.
- Added French translation. Special thanks to Nicolas Maltais who
  provided the translation.
- Added a "Not Connected" component to output a constant high-z value.
- If a high-z value is connected to a logic gate input, the read value
  is undefined.
- Improved debugging: It is possible to set the circuit to the
  state of a certain test result, by simply clicking on it.
- Generic circuits are easier to debug: It is possible now to create
  a specific, concrete circuit from a generic one.
- In generic circuits it is now possible to add components and
  wires to the circuit programmatically.
- It is now possible to use a probe as output in a test case.
- Adds undo to text fields
- If IEEE shapes are selected in the settings, also the CircuitBuilder
  uses wide shapes in the created circuits.
- Fixed a bug in the Demuxer Verilog template that causes problems
  when using multiple demuxers in the same circuit.
- Fixed a bug in the value editor, which occurs, if high-z is the
  default value of an input.
- Fixed an issue which avoids to restart a running simulation by just
  click on the start button again.
- Added IC 74190 to the Library.