RISC-V-Logisim-models

Simple RISC-V subset implementations for Computer Arhitecture course, Logisim Evolution-compatible. The goal of the project is to create the simple and easy-to understand RV32I architecture models for explaining the basics of computer design. RV0 is the reduced subset, supporting only arithmetic/logic/shift, Bcc, LW and SW instructions. RV1 (work in progress) is rv0 + JAL, JALR, LUI and AUIPC.