- Clean z80 files (not test dir)

- Add CPU, APU, PPU, DMA and top.v
fjpolo · May 28, 2024 · fca117b · fca117b
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diff --git a/README.md b/README.md
@@ -53,13 +53,13 @@ Browse [issues](https://github.com/rejunity/z80-open-silicon/issues).
 For project overview, take a look at the [slide deck](https://docs.google.com/presentation/d/1-vcqAm9nMe9o_P5PAofOEgkbrVqfZs-Lbs7DuWj7h2o/edit#slide=id.p) and [video](https://www.youtube.com/watch?v=GI1e22A2J3U) where we discuss FOSS Z80 project with Matthew Venn.
 
 Code:
-* You can find the top module in [src/tt_um_rejunity_z80.v](src/tt_um_rejunity_z80.v). It instantiates Z80 and adheres to [TinyTapeout constraints](https://tinytapeout.com/specs/gpio/) including multiplexing the output pins onto the 8 pins of TinyTapeout chip.
+* You can find the top module in [src/tt_um_fjpolo_r2a03.v](src/tt_um_fjpolo_r2a03.v). It instantiates Z80 and adheres to [TinyTapeout constraints](https://tinytapeout.com/specs/gpio/) including multiplexing the output pins onto the 8 pins of TinyTapeout chip.
 * The core Verilog Z80 implementation is in [src/tv80](src/tv80) folder.
 * The configuration for [OpenROAD](https://theopenroadproject.org) synthesis and place-and-route flow is in the [src/config.tcl](src/config.tcl) file.
 * Finally, the testbench is implemented in [src/test/test.py](src/test/test.py).
 
 Generated layout artifacts are in [gds](gds) folder. You can use [KLayout](https://www.klayout.de) viewer to inspect them:
-* [GDSII file of Z80 core](gds/tinytapeout_07_skywater130A/tt_um_rejunity_z80.gds)
+* [GDSII file of Z80 core](gds/tinytapeout_07_skywater130A/tt_um_fjpolo_r2a03.gds)
 * [OASIS file of the Tiny Tapeout 07 chip with the Z80 core](gds/tinytapeout_07_skywater130A/caravel_24066810.oas)
 
 ## Run it locally

diff --git a/docs/2x2_tiles.png b/docs/2x2_tiles.png
diff --git a/docs/3x2_tiles.png b/docs/3x2_tiles.png
diff --git a/docs/4x2_tiles.png b/docs/4x2_tiles.png
diff --git a/docs/Z8400_Z84C00_Product_Specification.pdf b/docs/Z8400_Z84C00_Product_Specification.pdf
diff --git a/docs/tt07_chip.png b/docs/tt07_chip.png
diff --git a/docs/tt07_chip_alt.png b/docs/tt07_chip_alt.png
diff --git a/docs/tt07_z80.png b/docs/tt07_z80.png
diff --git a/docs/z80-pinout-from-Zilog-Data-Book.png b/docs/z80-pinout-from-Zilog-Data-Book.png
diff --git a/gds/tinytapeout_07_skywater130A/tt_um_rejunity_z80.lef b/gds/tinytapeout_07_skywater130A/tt_um_rejunity_z80.lef
@@ -2,9 +2,9 @@ VERSION 5.7 ;
   NOWIREEXTENSIONATPIN ON ;
   DIVIDERCHAR "/" ;
   BUSBITCHARS "[]" ;
-MACRO tt_um_rejunity_z80
+MACRO tt_um_fjpolo_r2a03
   CLASS BLOCK ;
-  FOREIGN tt_um_rejunity_z80 ;
+  FOREIGN tt_um_fjpolo_r2a03 ;
   ORIGIN 0.000 0.000 ;
   SIZE 334.880 BY 225.760 ;
   PIN VGND
@@ -487,6 +487,6 @@ MACRO tt_um_rejunity_z80
         RECT 250.680 2.080 317.105 223.680 ;
         RECT 3.975 0.175 317.105 2.080 ;
   END
-END tt_um_rejunity_z80
+END tt_um_fjpolo_r2a03
 END LIBRARY
 
diff --git a/info.yaml b/info.yaml
@@ -1,26 +1,29 @@
 # Tiny Tapeout project information
 project:
-  title:        "Zilog Z80"      # Project title
-  author:       "ReJ aka Renaldas Zioma"      # Your name
-  discord:      "rzioma"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80."      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     16000000       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "Ricoh 2A03"                                                                            # Project title
+  author:       "@fjpolo  "                                                                             # Your name
+  discord:      "@fjpolo"                                                                               # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Ricoh 2A03 open-source silicon. This is a toy project towards FamiCom emulation."      # One line description of what your project does
+  language:     "Verilog"                                                                               # Other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     16000000                                                                                # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "4x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_rejunity_z80"      # Your top module name
+  top_module:  "tt_um_fjpolo_r2a03"                                                                     # Your top module name
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:
-    - "tv80/tv80_alu.v"
-    - "tv80/tv80_reg.v"
-    - "tv80/tv80_mcode.v"
-    - "tv80/tv80_core.v"
-    - "tv80/tv80s.v"
-    - "tt_um_rejunity_z80.v"
+    - "R2A03/apu.v"
+    - "R2A03/dma.v"
+    - "R2A03/ppu.v"
+    - "R2A03/top.v"
+    - "R2A03/t65/T65_ALU.v"
+    - "R2A03/t65/T65_MCode.v"
+    - "R2A03/t65/T65_Pack.v"
+    - "R2A03/t65/T65.v"
+    - "tt_um_fjpolo_r2a03.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

diff --git a/src/.gitignore b/src/.gitignore
diff --git a/src/R2A03/.gitignore b/src/R2A03/.gitignore