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yosys-tcl-ui-report
yosys-tcl-ui-report Public5 Day TCL begginer to advanced training workshop by VSD
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soc-design-and-planning-nasscom-vsd
soc-design-and-planning-nasscom-vsd Public2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
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advanced-pd-using-openlane-sky130
advanced-pd-using-openlane-sky130 Public2 Week Advanced Physical Design using OpenLANE/Sky130 workshop with complete RTL2GDSII flow organised by VSD as part of Level-3 of Chip Design for High School Program in collaboration with Intel India
Verilog 3
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btech-mini-project
btech-mini-project PublicThis was my BTech degree Mini-Project during semester 5 and it is an electronic lock which can be unlocked from anywhere.
HTML 1
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risc-v-myth-report
risc-v-myth-report Public5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD
Verilog
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