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Merge pull request #60 from ogamespec/main
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SanityCheck by @nukeykt
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ogamespec authored Apr 15, 2024
2 parents bac60f3 + 42fa9a4 commit 881579b
Showing 1 changed file with 34 additions and 0 deletions.
34 changes: 34 additions & 0 deletions Deroute/GetVerilog.cs
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,8 @@ public static string EntitiesToVerilogSource(EntityBox ebox, string top_module_n
string mod_prefix = top.module_name.ToLower() + "_";
instances = GetInstances(ents, mod_prefix);

SanityCheck(top, instances, wires);

// Output the verilog

string text = GetVerilogText(top, instances, wires, true) + GetModulesVerilog(instances);
Expand Down Expand Up @@ -417,5 +419,37 @@ static string IsConstantScalar (FutureWire wire)
}
return null;
}

static void SanityCheck (FutureInstance top, List<FutureInstance> instances, List<FutureWire> wires)
{
foreach (var wire in wires)
{
int input_ports = 0;
int output_ports = 0;
foreach (var e in wire.parts)
{
if (top.ports.Contains(e))
{
if (e.Type == EntityType.ViasOutput)
input_ports++;
if (e.Type == EntityType.ViasInput)
output_ports++;
}
else
{
if (e.Type == EntityType.ViasOutput)
output_ports++;
if (e.Type == EntityType.ViasInput)
input_ports++;
}
}
if (output_ports > 1)
Console.WriteLine("ERROR: conflicting wire {0}!!!", wire.name);
if (output_ports == 0 && input_ports > 0)
Console.WriteLine("ERROR: floating wire {0}!!!", wire.name);
if (output_ports == 1 && input_ports == 0)
Console.WriteLine("WARNING: wire not driving anything {0}!!!", wire.name);
}
}
}
}

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