[Core/CD] Fix various MCD registers, based on the hardware manual and mcd-verificator (#408) #464
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Fixes a number of errors reported by mcd-verificator (#408). Half is just simple bit masks to prevent unused bits from being written/read.
The other has to do with how the CDC register select and read/write actually functions. According to mcd-verificator, bit 4 in the CDC register select register is the "RS" flag, which you can read up on Sanyo LC8950/LC8951 manual. Interestingly, it seems that when the CDC register ID wraps back to 0 from 0xF, it'll actually switch the RS flag, effectively making it act as sort of a 5th bit? From the tests done in mcd-verificator, it seems to just act as an access enable flag of sorts? The LC8950 manual says that the RS flag is for dictating how registers are accessed (low ="direct addressing"/"AR", high = "indirect addressing"/"the register pointed to by AR", which I guess is for setups where you would switch between setting the register ID and register data within the same address, which isn't applicable to the MCD, since the 2 are split). The current implementation is based on what mcd-verificator has perceived it. Also, even if the register select is set to 0, it'll still increment on a register read/write if the RS flag is set. It'll only not increment if it's clear.
Minus the timing test errors, register X002 and the CDC register select/register data registers are reported as working correctly in mcd-verificator.