adding cace support plus removing unnecessary pins

[areda0]

• a .yaml file supporting latest CACE format was created
• extra CACE conditions for ena, vref_ext, vref_sel were added
• extra DVDD and DVSS pins in both sch, layout, and symbol views were removed
• the template tb was updated with CACE substitutions and measure statement was edited
• files locations were adapted to match the standard CACE files hierarchy
• LVS script for netgen_lvs was added

Summary:
With these changes the block passes: LVS , magic_drc , klayout_drc_full.
Area is measured but there isn't a spec to be compared against
The block tb doesn't include a load cap
Block still needs some work on the relevant specs verification (creating missing tbs and adding missing measurements)

[RTimothyEdwards]

Removing DVDD and DVSS is not correct. They are definitely part of the schematic and layout.

[RTimothyEdwards]

This cannot be merged. Pins DVDD and DVSS were very much part of the circuit and cannot be removed without breaking the whole circuit. Please fix.