added config.json

lvs/user_project_wrapper/lvs_config.json

@@ -0,0 +1,30 @@
+{
+    "TOP_SOURCE": "user_project_wrapper",
+    "TOP_LAYOUT": "$TOP_SOURCE",
+    "EXTRACT_FLATGLOB": [
+        ""
+    ],
+    "EXTRACT_ABSTRACT": [
+        "*__fill_*",
+        "*__fakediode_*",
+        "*__tapvpwrvgnd_*"
+    ],
+    "LVS_FLATTEN": [
+        ""
+    ],
+    "LVS_NOFLATTEN": [
+        ""
+    ],
+    "LVS_IGNORE": [
+        ""
+    ],
+    "LVS_SPICE_FILES": [
+        "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
+        "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+    ],
+    "LVS_VERILOG_FILES": [
+        "$UPRJ_ROOT/verilog/gl/user_proj_example.v",
+        "$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
+    ],
+    "LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
+}

openlane/user_proj_example/config.json

@@ -0,0 +1,29 @@
+{
+	"PDK": "gf180mcuC",
+	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+	"DESIGN_NAME": "user_proj_example",
+	"VERILOG_FILES": [
+		"dir::../../verilog/rtl/defines.v",
+		"dir::../../verilog/rtl/user_proj_example.v"
+	],
+	"DESIGN_IS_CORE": 0,
+	"CLOCK_PORT": "wb_clk_i",
+	"CLOCK_NET": "counter.clk",
+	"CLOCK_PERIOD": "24.0",
+	"FP_SIZING": "absolute",
+	"DIE_AREA": "0 0 900 600",
+	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"PL_BASIC_PLACEMENT": 0,
+	"PL_TARGET_DENSITY": 0.45,
+	"FP_CORE_UTIL": 40,
+	"SYNTH_MAX_FANOUT": 4,
+	"RT_MAX_LAYER": "met4",
+	"VDD_NETS": [
+		"vccd1"
+	],
+	"GND_NETS": [
+		"vssd1"
+	],
+	"DIODE_INSERTION_STRATEGY": 4,
+	"RUN_CVC": 1
+}

openlane/user_project_wrapper/config.json

@@ -0,0 +1,63 @@
+{
+	"PDK": "gf180mcuC",
+	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+	"VERILOG_FILES": [
+		"dir::../../verilog/rtl/defines.v",
+		"dir::../../verilog/rtl/user_project_wrapper.v"
+	],
+	"CLOCK_PORT": "user_clock2",
+	"CLOCK_NET": "mprj.clk",
+	"CLOCK_PERIOD": "10",
+	"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
+	"MACRO_PLACEMENT_CFG": "macro.cfg",
+	"VERILOG_FILES_BLACKBOX": [
+		"dir::../../verilog/gl/user_proj_example.v"
+	],
+	"FP_PDN_CHECK_NODES": 0,
+	"SYNTH_ELABORATE_ONLY": 1,
+	"PL_RANDOM_GLB_PLACEMENT": 1,
+	"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
+	"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
+	"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
+	"PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
+	"FP_PDN_ENABLE_RAILS": 0,
+	"DIODE_INSERTION_STRATEGY": 0,
+	"RUN_FILL_INSERTION": 0,
+	"RUN_TAP_DECAP_INSERTION": 0,
+	"CLOCK_TREE_SYNTH": 0,
+	"MAGIC_ZEROIZE_ORIGIN": 0,
+	"FP_SIZING": "absolute",
+	"DIE_AREA": "0 0 2980.2 2980.2",
+	"CORE_AREA": "12 12 2968.2 2968.2",
+	"RUN_CVC": 0,
+	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"UNIT": 2.4,
+	"FP_IO_VEXTEND": "expr::2 * $UNIT",
+	"FP_IO_HEXTEND": "expr::2 * $UNIT",
+	"FP_IO_VLENGTH": "expr::$UNIT",
+	"FP_IO_HLENGTH": "expr::$UNIT",
+	"FP_IO_VTHICKNESS_MULT": 4,
+	"FP_IO_HTHICKNESS_MULT": 4,
+	"FP_PDN_CORE_RING": 1,
+	"FP_PDN_CORE_RING_VWIDTH": 3.1,
+	"FP_PDN_CORE_RING_HWIDTH": 3.1,
+	"FP_PDN_CORE_RING_VOFFSET": 14,
+	"FP_PDN_CORE_RING_HOFFSET": 16,
+	"FP_PDN_CORE_RING_VSPACING": 1.7,
+	"FP_PDN_CORE_RING_HSPACING": 1.7,
+	"FP_PDN_HOFFSET": 5,
+	"FP_PDN_HPITCH_MULT": 1,
+	"FP_PDN_HPITCH": "expr::60 + $FP_PDN_HPITCH_MULT * 30",
+	"FP_PDN_VWIDTH": 3.1,
+	"FP_PDN_HWIDTH": 3.1,
+	"FP_PDN_VSPACING": "expr::5 * $FP_PDN_CORE_RING_VWIDTH",
+	"FP_PDN_HSPACING": 26.9,
+	"VDD_NETS": [
+		"vdd"
+	],
+	"GND_NETS": [
+		"vss"
+	],
+	"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
+	"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def"
+}