updated config file for wrapper

efabless · Oct 16, 2023 · c2dee2c · c2dee2c
1 parent c24d67d
commit c2dee2c
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Showing 2 changed files with 8 additions and 9 deletions.
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
@@ -6,9 +6,9 @@
 		"dir::../../verilog/rtl/defines.v",
 		"dir::../../verilog/rtl/user_project_wrapper.v"
 	],
-	"CLOCK_PORT": "user_clock2",
+	"CLOCK_PORT": "wb_clk_i",
 	"CLOCK_NET": "mprj.clk",
-	"CLOCK_PERIOD": "10",
+	"CLOCK_PERIOD": 25,
 	"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
 	"VERILOG_FILES_BLACKBOX": [
 		"dir::../../verilog/gl/user_proj_example.v"
@@ -75,6 +75,5 @@
 	],
 	"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
 	"RUN_LINTER": 0,
-	"QUIT_ON_TIMING_VIOLATIONS": 0,
 	"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def"
 }
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
@@ -94,11 +94,11 @@ module user_proj_example #(
 
     // LA
     assign la_data_out = {{(64-BITS){1'b0}}, count};
-    // Assuming LA probes [32:16] are for controlling the count register  
-    assign la_write = ~la_oenb[32:16] & ~{BITS{valid}};
-    // Assuming LA probes [34:33] are for controlling the count clk & reset  
-    assign clk = (~la_oenb[33]) ? la_data_in[33]: wb_clk_i;
-    assign rst = (~la_oenb[34]) ? la_data_in[34]: wb_rst_i;
+    // Assuming LA probes [61:46] are for controlling the count register  
+    assign la_write = ~la_oenb[61:62-BITS] & ~{BITS{valid}};
+    // Assuming LA probes [63:62] are for controlling the count clk & reset  
+    assign clk = (~la_oenb[62]) ? la_data_in[62]: wb_clk_i;
+    assign rst = (~la_oenb[63]) ? la_data_in[63]: wb_rst_i;
 
     counter #(
         .BITS(BITS)
@@ -111,7 +111,7 @@ module user_proj_example #(
         .wdata(wbs_dat_i[BITS-1:0]),
         .wstrb(wstrb),
         .la_write(la_write),
-        .la_input(la_data_in[31:32-BITS]),
+        .la_input(la_data_in[61:62-BITS]),
         .count(count)
     );