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add timing reports [skip ci]
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@kareefardi
kareefardi committed Aug 27, 2023
1 parent fab698c commit 761470a
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9 changes: 9 additions & 0 deletions signoff/user_proj_example/openlane-signoff/timing-reports/COMMANDS
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sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
sta -no_splash -exit /nix/store/ixkawr2rm870iw9p31jr6cicdswgpcx8-python3-3.10.9-env/lib/python3.10/site-packages/openlane/scripts/openroad/sta/corner.tcl
191 changes: 191 additions & 0 deletions signoff/user_proj_example/openlane-signoff/timing-reports/config.json
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{
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"VDD_PIN": "VPWR",
"GND_PIN": "VGND",
"WIRE_LENGTH_THRESHOLD": null,
"TECH_LEFS": {
"nom_*": "/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef",
"min_*": "/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef",
"max_*": "/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"
},
"GPIO_PADS_LEF": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"
],
"GPIO_PADS_LEF_CORE_SIDE": [
"/home/karim/work/pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef",
"/home/karim/work/pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"
],
"GPIO_PADS_VERILOG": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
],
"GPIO_PADS_PREFIX": [
"sky130_fd_io",
"sky130_ef_io"
],
"PRIMARY_SIGNOFF_TOOL": "magic",
"DEFAULT_MAX_TRAN": null,
"DATA_WIRE_RC_LAYER": "met2",
"CLOCK_WIRE_RC_LAYER": "met5",
"DEFAULT_CORNER": "nom_tt_025C_1v80",
"STA_CORNERS": [
"nom_tt_025C_1v80",
"nom_ss_100C_1v60",
"nom_ff_n40C_1v95",
"min_tt_025C_1v80",
"min_ss_100C_1v60",
"min_ff_n40C_1v95",
"max_tt_025C_1v80",
"max_ss_100C_1v60",
"max_ff_n40C_1v95"
],
"FP_TRACKS_INFO": "/home/karim/work/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info",
"FP_TAPCELL_DIST": 13,
"FP_PDN_RAIL_OFFSET": 0,
"FP_PDN_VWIDTH": 1.6,
"FP_PDN_VSPACING": 1.7,
"FP_PDN_HSPACING": 1.7,
"FP_PDN_HWIDTH": 1.6,
"FP_PDN_CORE_RING_VWIDTH": 1.6,
"FP_PDN_CORE_RING_HWIDTH": 1.6,
"FP_PDN_CORE_RING_VSPACING": 1.7,
"FP_PDN_CORE_RING_HSPACING": 1.7,
"FP_PDN_CORE_RING_VOFFSET": 6,
"FP_PDN_CORE_RING_HOFFSET": 6,
"FP_IO_HLAYER": "met3",
"FP_IO_VLAYER": "met2",
"RT_MIN_LAYER": "met1",
"RT_MAX_LAYER": "met4",
"SCL_GROUND_PINS": [
"VGND",
"VNB"
],
"SCL_POWER_PINS": [
"VPWR",
"VPB"
],
"FILL_CELL": [
"sky130_fd_sc_hd__fill*"
],
"DECAP_CELL": [
"sky130_ef_sc_hd__decap_12",
"sky130_fd_sc_hd__decap_8",
"sky130_fd_sc_hd__decap_6",
"sky130_fd_sc_hd__decap_4",
"sky130_fd_sc_hd__decap_3"
],
"LIB": {
"*_tt_025C_1v80": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
],
"*_ss_100C_1v60": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
],
"*_ff_n40C_1v95": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
]
},
"CELL_LEFS": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef"
],
"CELL_GDS": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds"
],
"CELL_SPICE_MODELS": [
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fakediode_2.spice",
"/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice"
],
"SYNTH_EXCLUSION_CELL_LIST": "/home/karim/work/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells",
"PNR_EXCLUSION_CELL_LIST": "/home/karim/work/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells",
"OUTPUT_CAP_LOAD": 33.442,
"MAX_FANOUT_CONSTRAINT": 16,
"MAX_TRANSITION_CONSTRAINT": 1,
"CLOCK_UNCERTAINTY_CONSTRAINT": 0.25,
"CLOCK_TRANSITION_CONSTRAINT": 0.15,
"TIME_DERATING_CONSTRAINT": 5,
"IO_DELAY_CONSTRAINT": 20,
"SYNTH_DRIVING_CELL": "sky130_fd_sc_hd__inv_2/Y",
"SYNTH_CLK_DRIVING_CELL": null,
"SYNTH_TIEHI_CELL": "sky130_fd_sc_hd__conb_1/HI",
"SYNTH_TIELO_CELL": "sky130_fd_sc_hd__conb_1/LO",
"SYNTH_BUFFER_CELL": "sky130_fd_sc_hd__buf_2/A/X",
"CTS_ROOT_BUFFER": "sky130_fd_sc_hd__clkbuf_16",
"CTS_CLK_BUFFERS": [
"sky130_fd_sc_hd__clkbuf_8",
"sky130_fd_sc_hd__clkbuf_4",
"sky130_fd_sc_hd__clkbuf_2"
],
"CTS_MAX_CAP": 1.53169,
"FP_WELLTAP_CELL": "sky130_fd_sc_hd__tapvpwrvgnd_1",
"FP_ENDCAP_CELL": "sky130_fd_sc_hd__decap_3",
"FP_PDN_RAIL_LAYER": "met1",
"FP_PDN_RAIL_WIDTH": 0.48,
"FP_PDN_HORIZONTAL_LAYER": "met5",
"FP_PDN_VERTICAL_LAYER": "met4",
"IGNORE_DISCONNECTED_MODULES": [
"sky130_fd_sc_hd__conb_1"
],
"PLACE_SITE": "unithd",
"PLACE_SITE_WIDTH": 0.46,
"PLACE_SITE_HEIGHT": 2.72,
"GPL_CELL_PADDING": 2,
"DPL_CELL_PADDING": 2,
"CELL_PAD_EXCLUDE": [
"sky130_fd_sc_hd__tap*",
"sky130_fd_sc_hd__decap*",
"sky130_ef_sc_hd__decap*",
"sky130_fd_sc_hd__fill*"
],
"DIODE_CELL": "sky130_fd_sc_hd__diode_2/DIODE",
"GRT_LAYER_ADJUSTMENTS": [
0.99,
0,
0,
0,
0,
0
],
"CVC_SCRIPTS_DIR": "/home/karim/work/pdk/sky130A/libs.tech/openlane/cvc",
"DESIGN_DIR": "/home/karim/work/caravel_user_project/openlane/user_proj_example",
"DESIGN_NAME": "user_proj_example",
"PDK_ROOT": "/home/karim/work/pdk",
"PDK": "sky130A",
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "counter.clk",
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"DIE_AREA": "0 0 2800 1760",
"MACROS": null,
"EXTRA_LEFS": null,
"EXTRA_VERILOG_MODELS": null,
"EXTRA_SPICE_MODELS": null,
"EXTRA_LIBS": null,
"EXTRA_GDS_FILES": null,
"FP_CONTEXT_DEF": null,
"FP_CONTEXT_LEF": null,
"FP_PADFRAME_CFG": null,
"GRT_OBS": null,
"LVS_INSERT_POWER_PINS": true,
"RUN_CVC": true,
"LEC_ENABLE": false,
"CHECK_ASSIGN_STATEMENTS": false,
"PDN_CONNECT_MACROS_TO_GRID": true,
"PDN_MACRO_CONNECTIONS": null,
"PDN_ENABLE_GLOBAL_CONNECTIONS": true,
"STA_MACRO_PRIORITIZE_NL": true,
"RUN_MCSTA": true,
"meta": {
"openlane_version": "2.0.0b10",
"step": "OpenROAD.STAPostPNR"
}
}
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