Merge pull request #317 from efabless/fix_cocotb_tests

fix the counter tests after latests RTL updates
efabless · Oct 23, 2023 · 1cbe00a · 1cbe00a
2 parents c913b37 + 607bd6f
commit 1cbe00a
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Showing 8 changed files with 29 additions and 12 deletions.
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.c b/verilog/dv/cocotb/gpio_test/gpio_test.c
@@ -22,9 +22,9 @@ void main(){
    //GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUT);
    GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUTPUT);
    GPIOs_loadConfigs();
-   set_gpio_l(0x8F);
+   GPIOs_writeLow(0x8F);
    ManagmentGpio_write(1); // configuration finished 
 
 
    return;
-}
+}
diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c
@@ -31,7 +31,7 @@ void main(){
     GPIOs_loadConfigs(); // load the configuration 
     ManagmentGpio_write(1); // configuration finished 
     // configure la [63:32] as output from cpu
-    LogicAnalyzer_write(1,7);
+    LogicAnalyzer_write(1,7<<16);
     LogicAnalyzer_outputEnable(1,0);
     ManagmentGpio_write(0); // configuration finished 
     LogicAnalyzer_outputEnable(1,0xFFFFFFFF);

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py
@@ -22,7 +22,7 @@
 @cocotb.test()
 @report_test
 async def counter_la(dut):
-    caravelEnv = await test_configure(dut,timeout_cycles=1346140)
+    caravelEnv = await test_configure(dut, timeout_cycles=59844)
 
     cocotb.log.info(f"[TEST] Start counter_la test")  
     # wait for start of sending
@@ -36,7 +36,7 @@ async def counter_la(dut):
     counter = overwrite_val
 
     if received_val != counter :
-        cocotb.log.fatal(f"LA writing is in correct: {overwrite_val} receieved: {received_val}")
+        cocotb.log.fatal(f"LA writing is incorrect: {overwrite_val} receieved: {received_val}")
     await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
 
     # wait until the LA writing is disabled 

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c
@@ -32,8 +32,16 @@ void main(){
     // configure la 64 (clk enable by la) as output from cpu
     // writing 1 in bit 64(first bit in reg 2) to reset 
     LogicAnalyzer_write(2,0);
-    LogicAnalyzer_inputEnable(2,0x1);
-    LogicAnalyzer_outputEnable(2,0xFFFFFFFE);
+    // LogicAnalyzer_inputEnable(2,0x1);
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFC);
+    // reset counter 
+    // reset 1
+    LogicAnalyzer_write(2,3); // clk pose edge
+    LogicAnalyzer_write(2,2);// clk pose edge
+    // reset 0
+    LogicAnalyzer_write(2,1); // clk pose edge
+    LogicAnalyzer_write(2,0);// clk pose edge
+
     ManagmentGpio_write(1); // configuration finished 
 
     for (int i = 0; i < 7; i++){

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py
@@ -22,7 +22,7 @@
 @cocotb.test()
 @report_test
 async def counter_la_clk(dut):
-    caravelEnv = await test_configure(dut,timeout_cycles=1346140)
+    caravelEnv = await test_configure(dut,timeout_cycles=61011)
 
     cocotb.log.info(f"[TEST] Start counter_wb test")  
     # wait for start of sending

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c
@@ -29,12 +29,19 @@ void main(){
     GPIOs_configure(36,GPIO_MODE_MGMT_STD_OUTPUT);
     GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT);
     GPIOs_loadConfigs(); // load the configuration 
+    // reset counter
+    LogicAnalyzer_outputEnable(2,0xFFFFFFFD);
+    LogicAnalyzer_write(2,2);
+    LogicAnalyzer_write(2,0);
+
     ManagmentGpio_write(1); // configuration finished 
     // configure la 65 (reset enable by la) as output from cpu
     // writing 1 in bit 65(second bit in reg 2) to reset 
+    // asset reset
     LogicAnalyzer_write(2,2);
     LogicAnalyzer_inputEnable(2,0x2);
     LogicAnalyzer_outputEnable(2,0xFFFFFFFD);
+    // deassert reset
     LogicAnalyzer_inputEnable(2,0);
     LogicAnalyzer_outputEnable(2,0xFFFFFFFF);
 

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c
@@ -25,8 +25,12 @@ void main(){
 
     GPIOs_loadConfigs(); // load the configuration 
     User_enableIF(); // this necessary when reading or writing between wishbone and user project if interface isn't enabled no ack would be recieve and the command will be stuck
+    // user la reset and wb clk
+    LogicAnalyzer_outputEnable(2,1);
+    // reset counter 
+    LogicAnalyzer_write(2,2);
+    LogicAnalyzer_write(2,0);
     ManagmentGpio_write(1); // configuration finished 
-
     // writing to any address inside user project address space would reload the counter value
     USER_writeWord(0x7,0x88);
     ManagmentGpio_write(0); // start counting from 0

diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py
@@ -22,7 +22,7 @@
 @cocotb.test()
 @report_test
 async def counter_wb(dut):
-    caravelEnv = await test_configure(dut,timeout_cycles=3346140)
+    caravelEnv = await test_configure(dut,timeout_cycles=22620)
 
     cocotb.log.info(f"[TEST] Start counter_wb test")  
     # wait for start of sending
@@ -33,8 +33,6 @@ async def counter_wb(dut):
     # expect value bigger than 7 
     received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)  
     counter = received_val
-    if received_val <= overwrite_val :
-        cocotb.log.error(f"Counter started late and value captured after configuration is smaller than overwrite value: {overwrite_val} receieved: {received_val}")
     await cocotb.triggers.ClockCycles(caravelEnv.clk,1)
 
     while True: # wait until the value 1 start counting after the initial