Update user_proj_example.v

style - keep all the constants in the same style with prepended width and type.
efabless · Oct 17, 2023 · 0854e4d · 0854e4d
1 parent c913b37
commit 0854e4d
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
@@ -134,12 +134,12 @@ module counter #(
 
     always @(posedge clk) begin
         if (reset) begin
-            count <= 0;
-            ready <= 0;
+            count <= 1'b0;
+            ready <= 1'b0;
         end else begin
             ready <= 1'b0;
             if (~|la_write) begin
-                count <= count + 1;
+                count <= count + 1'b1;
             end
             if (valid && !ready) begin
                 ready <= 1'b1;