Verilog and layout for Caravel Openframe #431
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open-frame version of Caravel.
layout has not been run through LVS yet; ongoing work.
The chip_io_openframe cell is now LVS clean except for a ground short which may not even be an error (and technically isn't one regardless). Modified pins so that all wrapper pins on right and left are on metal 3, and all wrapper pins on top and bottom (except power pins) are on metal 2, to facilitate digital routing.
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@jeffdi : Since you merged |
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Yes - thanks Tim. Ping me when ready and I will merge right away.
…-- Jeff
On Mon, May 8, 2023 at 12:51 PM R. Timothy Edwards ***@***.***> wrote:
@jeffdi <https://github.com/jeffdi> : Since you merged caravel-redesign-2
into main without doing this merge, it will probably work better now if I
copy these files into main and regenerate the pull request.
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New pull request is #451. After pulling, please close this pull request. |
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@jeffdi : ping. |
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@jeffdi : ping? |
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Added verilog and layout for the latest specification of the open-frame version of Caravel.