Added pins "vddio" and "vssio" to the openframe and openframe project

wrapper RTL netlists and and openframe project wrapper GL netlist.
efabless · Oct 18, 2023 · 4cd9d9c · 4cd9d9c
1 parent 15bd09f
commit 4cd9d9c
Show file tree

Hide file tree

Showing 3 changed files with 10 additions and 2 deletions.
diff --git a/verilog/gl/caravel_openframe-example.v b/verilog/gl/caravel_openframe-example.v
@@ -1016,6 +1016,8 @@ module caravel_openframe(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd,
     .resetb_h(rstb_h),
     .resetb_l(rstb_l),
     .vccd1(vccd1_core),
-    .vssd1(vssd1_core)
+    .vssd1(vssd1_core),
+    .vddio(vddio_core),
+    .vssio(vssio_core)
   );
 endmodule
diff --git a/verilog/gl/caravel_openframe.v b/verilog/gl/caravel_openframe.v
@@ -1026,6 +1026,8 @@ module caravel_openframe(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd,
     .vssa2(vssa2_core),
     .vssd(vssd_core),
     .vssd1(vssd1_core),
-    .vssd2(vssd2_core)
+    .vssd2(vssd2_core),
+    .vddio(vddio_core),
+    .vssio(vssio_core)
   );
 endmodule
diff --git a/verilog/rtl/__openframe_project_wrapper.v b/verilog/rtl/__openframe_project_wrapper.v
@@ -43,6 +43,8 @@ module openframe_project_wrapper (
     inout vssd,		// Common digital ground
     inout vssd1,	// User area 1 digital ground
     inout vssd2,	// User area 2 digital ground
+    inout vddio,	// Common 3.3V ESD supply
+    inout vssio,	// Common ESD ground
 `endif
 
     /* Signals exported from the frame area to the user project */
@@ -116,6 +118,8 @@ module openframe_project_wrapper (
 		.vssd(vssd),
 		.vssd1(vssd1),
 		.vssd2(vssd2),
+		.vddio(vddio),
+		.vssio(vssio),
 `endif
 	    .porb_h(porb_h),
 	    .porb_l(porb_l),