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x86: use OMR option to disable CPU features
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Signed-off-by: Bradley Wood <[email protected]>
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BradleyWood committed Dec 5, 2024
1 parent ef98195 commit fcb63d9
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Showing 2 changed files with 3 additions and 26 deletions.
3 changes: 0 additions & 3 deletions runtime/compiler/x/codegen/J9CodeGenerator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -99,9 +99,6 @@ J9::X86::CodeGenerator::initialize()
cg->setSupportsInliningOfTypeCoersionMethods();
cg->setSupportsNewInstanceImplOpt();

TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1) == cg->getX86ProcessorInfo().supportsSSE4_1(), "supportsSSE4_1() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSSE3) == cg->getX86ProcessorInfo().supportsSSSE3(), "supportsSSSE3() failed\n");

if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE4_1) &&
!comp->getOption(TR_DisableSIMDStringCaseConv) &&
!TR::Compiler->om.canGenerateArraylets() && !TR::Compiler->om.isOffHeapAllocationEnabled())
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26 changes: 3 additions & 23 deletions runtime/compiler/x/env/J9CPU.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -139,36 +139,16 @@ J9::X86::CPU::supportsFeature(uint32_t feature)
{
OMRPORT_ACCESS_FROM_OMRPORT(TR::Compiler->omrPortLib);

if (is_feature_disabled(feature))
return false;

static bool disableCPUDetectionTest = feGetEnv("TR_DisableCPUDetectionTest");
if (!disableCPUDetectionTest)
{
TR_ASSERT_FATAL(self()->supports_feature_test(feature), "Old API and new API did not match: processor feature %d\n", feature);
TR_ASSERT_FATAL(TRUE == omrsysinfo_processor_has_feature(&_supportedFeatureMasks, feature), "New processor feature usage detected, please add feature %d to _supportedFeatureMasks via TR::CPU::enableFeatureMasks()\n", feature);
}

static bool disableAVX512 = feGetEnv("TR_DisableAVX512");

if (disableAVX512)
{
switch (feature)
{
case OMR_FEATURE_X86_AVX512F:
case OMR_FEATURE_X86_AVX512VL:
case OMR_FEATURE_X86_AVX512BW:
case OMR_FEATURE_X86_AVX512DQ:
case OMR_FEATURE_X86_AVX512CD:
case OMR_FEATURE_X86_AVX512ER:
case OMR_FEATURE_X86_AVX512PF:
case OMR_FEATURE_X86_AVX512_BITALG:
case OMR_FEATURE_X86_AVX512_IFMA:
case OMR_FEATURE_X86_AVX512_VBMI:
case OMR_FEATURE_X86_AVX512_VBMI2:
case OMR_FEATURE_X86_AVX512_VNNI:
case OMR_FEATURE_X86_AVX512_VPOPCNTDQ:
return false;
}
}

return TRUE == omrsysinfo_processor_has_feature(&_processorDescription, feature);
}

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