Skip to content

Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.

License

Notifications You must be signed in to change notification settings

dusanerdeljan/riscv-toolchain

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

31 Commits
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

RISC-V Toolchain

Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler. Required programs for setting up the toolchain are flex, bison, gcc and make.

Compiler

Compiler supports a limited subset of the C language (called Micro-C) and generates RV32I assembly code.

Compilation

Run make in the riscv-toolchain/compiler directory.

Example usage

./micro_riscv < example-file.mc

image

Simulator

Simulator supports RV32I instruction set.

Compilation

Run make in the riscv-toolchain/simulator directory.

Options

Options are:

  • -r Only print the result, without running the interactive mode
  • -s Maximum number of instructions a simulator can execute

If no options are given, simulator will run in interactive mode for the maxmimum of 2000 instructions.

Example usage

./riscvsim < sum_up_to.s

image

Disassembler

Disassembler supports RV64GC instruction sets and is made for testing wether the given program is compatible for execution on a Linux-compatible processor/microcontroller which supports given instruction sets.

Compilation

Run make compile in the riscv-toolchain/disassembler directory.

Options

Options are:

  • -t X Architecture type, where X is 32/64/128
  • -i Disassembles RVXI (base integer) instruction set
  • -f Disassembles RVXF (single-precision, floating-point) standard extension
  • -a Disassembles RVXA (atomic) standard extension
  • -m Disassembles RVXM (multiplication) standard extension
  • -d Disassembles RVXD (double-precision, floating-point, requires F standard extension) standard extension
  • -c Disassembles RVXC (compressed) instruction set
  • -e Disassembles RV32E (can only be combined with M,A,C standard extensions, used on embedded systems) instruction set
  • -q Disassembles RV128Q (quad-precision, floating-point, requires RV64IFD instruction set) extension
  • -h Show help

If no options are given the default instruction set is RV64GC (RV64IFAMDC)

Example usage

./rv64dis examples/example4.bin

image

License

This program is free.
You can redistribute it and/or change it under the terms of GNU General Public License version 3.0 (GPLv3).
You can find the copy of the license in the repository.

About

Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.

Topics

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published