[WIP] [RISCV][SG2042] feat: add sg2042 support #399
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Signed-off-by: Xiaoguang Xing <[email protected]>
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Signed-off-by: Xiaoguang Xing <[email protected]>
The standardized Zicbom extension supports only VA, however there's some vendor extensions (e.g. XtheadCmo) that can handle cache management operations on PA directly, bypassing the TLB lookup. Add a CMO alternatives macro variant that come with both VA and PA supplied, and the code can be patched to use either the VA or the PA at runtime. In this case the codepath is now patched to use VA for Zicbom and PA for XtheadCmo. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Guo Ren <[email protected]>
DMA synchorization is done on PA and the VA is calculated from the PA. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Guo Ren <[email protected]>
When doing DMA page preparation, both the VA and the PA are easily accessible from struct page. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Originall the T-Head PBMT implementation in the kernel is intended for D1, thus the Sharable bit is not set. In addition, the Bufferable bit is not set for writecombine situation. Set these bits in the T-Head PBMT attributes definition. Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Fix qspinlock issue that loops to call cpu_relax and not exit. The call trace is: queued_spin_lock_slowpath->arch_mcs_spin_lock_contended ->smp_cond_load_acquire. RISCV has not defined smp_cond_load_acquire, so it uses generic funtion that defined in include/asm-generic/barrier.h. The generic smp_cond_load_acquire calls smp_cond_load_relaxed that loops to call READ_ONCE and cpu_relax. The READ_ONCE need barrier after it to get the new value.
Fix T-Head C9xx store merge buffer delay problem Signed-off-by: haijiao.liu <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Sophgo SPI Flash Master Controller (SPIFMC) is a master controller to control serial SPI Flash. Enable CONFIG_SPI_SOPHGO_SPIFMC if you have a device with a SPIFMC controller and want to access the Flash as a mtd device. There is GD25LB512ME Serial Flash on SG2042 EVB, controlled by SPIFMC. Signed-off-by: jingyu.li01 <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Signed-off-by: fengchun.li <[email protected]>
Turn on msi-x for top intr. Create msi-x whitelist, Limited the number of msi-x interrupts for inter x520 and wangxun NIC. Signed-off-by: chengjun.li <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Xiaoguang Xing <[email protected]>
This is needed to support recent hardware in the amdgpu DRM driver. The FPU code in that driver is not performance-critical, so only provide the minimal support. Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]>
Since it is not possible to incrementally add/remove extensions from the compiler's ISA string by appending arguments, any code that wants to modify the ISA string must recreate the whole thing. To support this, factor out the logic for generating the -march argument so it can be reused where needed. Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]>
RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other architectures. Enabling hardware FP requires overriding the ISA string for the relevant compilation units. Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]>
The bug is triggered when run WARN_ON_ONCE(is_migration_disabled(p)). [ 3298.725394] WARNING: CPU: 73 PID: 0 at kernel/sched/core.c:3147 set_task_cpu+0x18a/0x18e [ 3298.733591] Modules linked in: nf_conntrack_netlink xt_addrtype xt_statistic xt_nat xt_MASQUERADE nft_chain_nat nf_nat xt_mark xt_conntrack xt_comment nft_compat tls nf_tables nfnetlink overlay rfkill qrtr sunrpc ofpart ipmi_si vfat sophgo_spifmc ipmi_devintf spi_nor fat ipmi_msghandler mtd uio_pdrv_genirq uio loop zram ast drm_vram_helper drm_ttm_helper spi_dw_mmio ixgbe spi_dw gpio_dwapb r8169 ttm mdio scsi_dh_rdac scsi_dh_emc scsi_dh_alua ip6_tables ip_tables dm_multipath ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 br_netfilter bridge stp llc [ 3298.785070] CPU: 73 PID: 0 Comm: swapper/73 Not tainted 6.1.31 deepin-community#1 [ 3298.791220] Hardware name: Sophgo Mango (DT) [ 3298.795504] epc : set_task_cpu+0x18a/0x18e [ 3298.799649] ra : load_balance+0x51c/0xb5c [ 3298.803766] epc : ffffffff8004cef6 ra : ffffffff8005dae0 sp : ffffffc80a60bab0 [ 3298.810995] gp : ffffffff81e75e48 tp : ffffffe7feaf1f40 t0 : ffffffc80a60bad0 [ 3298.818216] t1 : 0000000002e2c8d6 t2 : 0000000008016002 s0 : ffffffc80a60baf0 [ 3298.825436] s1 : fffffff00038ddc0 a0 : fffffff00038ddc0 a1 : 000000000000002d [ 3298.832659] a2 : fffffffffe45afe4 a3 : 0000000000000000 a4 : ffffffff81e9c098 [ 3298.839878] a5 : 0000000000000001 a6 : 0000000000000001 a7 : ffffffffffffffff [ 3298.847099] s2 : fffffff00038dea8 s3 : 000000000000002d s4 : 000000000000002d [ 3298.854320] s5 : fffffff65f4fe800 s6 : ffffffff81efb588 s7 : 0000000000000001 [ 3298.861539] s8 : 0000000000000002 s9 : ffffffff81e75d78 s10: ffffffc80a60bbc0 [ 3298.868757] s11: fffffff65f4fe800 t3 : 0000000002845dfc t4 : 00000000000065f9 [ 3298.875983] t5 : 0000000000013dc2 t6 : 000000000000032e [ 3298.881294] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 [ 3298.889211] [<ffffffff8004cef6>] set_task_cpu+0x18a/0x18e [ 3298.894621] [<ffffffff8005dae0>] load_balance+0x51c/0xb5c [ 3298.900026] [<ffffffff8005eb52>] rebalance_domains+0x1f0/0x382 [ 3298.905862] [<ffffffff8005f094>] run_rebalance_domains+0x6a/0x8a [ 3298.911869] [<ffffffff80c6d04c>] __do_softirq+0x18c/0x336 [ 3298.917280] [<ffffffff80020990>] __irq_exit_rcu+0x116/0x148 [ 3298.922866] [<ffffffff80020b22>] irq_exit+0x18/0x28 [ 3298.927745] [<ffffffff80c62c96>] generic_handle_arch_irq+0x64/0x74 [ 3298.933929] [<ffffffff80003dbc>] ret_from_exception+0x0/0x16 [ 3298.939595] [<ffffffff80c62f52>] ct_idle_enter+0x12/0x1a [ 3298.944912] ---[ end trace 0000000000000000 ]--- Signed-off-by: Xiaoguang Xing <[email protected]>
These are loop counters which is inherently unsigned. Therefore make them unsigned. Moreover it also fixes alloc-size-larger-than error with gcc-13, where malloc can be called with (-1) due to tmp_len being an int type. Fixes | cpumap.c:366:20: error: argument 1 range [18446744065119617024, 18446744073709551612] exceeds maximum object size 9223372036854775807 [-Werror=alloc-size-larger-than=] | 366 | tmp_cpus = malloc(tmp_len * sizeof(struct perf_cpu)); | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Khem Raj <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Upstream-Status: Submitted [https://lore.kernel.org/linux-perf-users/[email protected]/T/#u]
Signed-off-by: Xiaoguang Xing <[email protected]>
dirvers:pci:remove the err log of parsing pci Signed-off-by: fengchun.li <[email protected]>
Modified the gpio clock-names in GPIO nodes so mango dts could adapt to Designware gpio controller driver, then gpio bus clock and gpio debounce clock would be enabled. I also force enable the gpio interrupt clock in sophgo clock system so that the gpio interrupt trigger could take effect. Signed-off-by: chunzhi.lin <[email protected]>
Signed-off-by: chunzhi.lin <[email protected]>
Signed-off-by: chunzhi.lin <[email protected]>
Signed-off-by: chunzhi.lin <[email protected]>
Basic functionalities have been tested to work fine on pioneer board.
Signed-off-by: lin peng <[email protected]>
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deepin pr auto reviewFix build error in RPi 3 Pipermail-Archive-2018-08.txt:
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opsiff
reviewed
Sep 3, 2024
| @@ -1109,6 +1109,8 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |||
| u16 cmd; | |||
| int r; | |||
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| return 0; | |||
opsiff
reviewed
Sep 3, 2024
RISCV SG2042没有PCIE缓存一致性 可能需要一个选项 |
opsiff
reviewed
Sep 3, 2024
| @@ -598,7 +598,7 @@ void pcie_port_service_unregister(struct pcie_port_service_driver *drv) | |||
| } | |||
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| /* If this switch is set, PCIe port native services should not be enabled. */ | |||
| bool pcie_ports_disabled; | |||
| bool pcie_ports_disabled = true; | |||
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该提交会导致其它架构编译失败，我先加上WIP标签，在问题解决后才可合并 |
Avenger-285714
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