This repository contains the Verilog development training files and provides workflow in a lab.
Promise: To Digital IC Design from scratch
Task | Detailed subtask |
---|---|
Design | Behavioral, Gate level, transistor-level |
Analysis of design | Timing, Power, Performance, Manufacturability, Testability, Reliability |
-
create a folder for development under designs_n_tb folder
-
create design file: design_module_name.v
iverilog design_module_name.v
- create test file: design_module_name_test.v this file has one line $dumpfile("dmn.vcd")
iverilog -o dmnx design_module_name_test.v
vvp dmnx
open -a gtkwave.app dmn.vcd
- push the design, testbench and results to github repository
git add -A
git commit -m "write message describing the changes made or if new desing is made"
git push
- Clone the repository
git clone https://github.com/Monk9Tech/Digital-Design-Development-Training.git
git switch -c "new-branch-contributer_name"
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modify and create new files
-
push to the new-branch-contributer_name
git push -u origin new-branch-contributer_name
No | Design module | Verilog file name | Learning objective |
---|---|---|---|
1 | Hello world display | use_display.v | To understand use of display and monitor |
2 | hierarchical modeling concepts | hierarchical_modeling.v | Design methodologies, design at different levels of abstractions |
3 | Counter | counter.v | To design counter and timer |
4 | Inverter | inverter.v | i/p o/p Ports, assign data flow statments |
5 | Half adder | half_adder.v | logic operation statements |
6 | Full adder | full_adder.v | more input ports |
7 | Full subtractor | full_subtractor.v | more diffrent functional logic modules |
8 | D flipflop | D_flipflop.v | sequential circuit, clock, clock generation, $finish system task |
9 | JK flipflop | JK_flipflop.v | with more than one input ports |
10 | Traffic light controller | traffic_light_controller.v | Timing from clock |
11 | Washing machine controller | 9_washing.. Top module - Microcontroller.v | Communication between two modules |
12 | Elevator controller | 10_lift/lift_controller.v | Top down design, differetn testbench |
13 | Substractor | 11_half_substractor, 12_full_substractor | |
14 | Multiplier | 13_multiplier | This is a high level behavioral modeling example |
15 | Random Access Memory | 14_memory | creating memory |
16 | CAN bus protocol | ||
17 | GPIO multiplier | ||
18 | Voltage regulator |
- Coffee machine
- Candy machine dispenser
- SoC
- Microprocessor/Microcontroller
- Digital and analog signal processor
- Graphics processor
- Neural processor
- Nvidia type - GPU
- Neuromorphic processor
- Mixed signal IC
- Book: Sumir Palnitkar, VLSI Design
- Tutorials point
- eSim tutorial
- Zero to ASIC
- VLSI design testing
- iverilog
A single point for the suite of open-source Electronic Design Automation tools including Magic, qflow, Netgen, IRSIM, PCB and XCircuit.
- Get efabless account for free.
- Main website - opencircuitdesign
- Open_pdks
- Magic VLSI Layout tool
- His github repos