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Digital-Design-Development-Training

This repository contains the Verilog development training files and provides workflow in a lab.

Promise: To Digital IC Design from scratch

Task Detailed subtask
Design Behavioral, Gate level, transistor-level
Analysis of design Timing, Power, Performance, Manufacturability, Testability, Reliability

Workflow (Design)

  1. create a folder for development under designs_n_tb folder

  2. create design file: design_module_name.v

iverilog design_module_name.v
  1. create test file: design_module_name_test.v this file has one line $dumpfile("dmn.vcd")
iverilog -o dmnx design_module_name_test.v
vvp dmnx
open -a gtkwave.app dmn.vcd
  1. push the design, testbench and results to github repository
git add -A
git commit -m "write message describing the changes made or if new desing is made"
git push

Workflow for contributors

  1. Clone the repository
git clone https://github.com/Monk9Tech/Digital-Design-Development-Training.git
git switch -c "new-branch-contributer_name"
  1. modify and create new files

  2. push to the new-branch-contributer_name

git push -u origin new-branch-contributer_name

Verilog design training steps

No Design module Verilog file name Learning objective
1 Hello world display use_display.v To understand use of display and monitor
2 hierarchical modeling concepts hierarchical_modeling.v Design methodologies, design at different levels of abstractions
3 Counter counter.v To design counter and timer
4 Inverter inverter.v i/p o/p Ports, assign data flow statments
5 Half adder half_adder.v logic operation statements
6 Full adder full_adder.v more input ports
7 Full subtractor full_subtractor.v more diffrent functional logic modules
8 D flipflop D_flipflop.v sequential circuit, clock, clock generation, $finish system task
9 JK flipflop JK_flipflop.v with more than one input ports
10 Traffic light controller traffic_light_controller.v Timing from clock
11 Washing machine controller 9_washing.. Top module - Microcontroller.v Communication between two modules
12 Elevator controller 10_lift/lift_controller.v Top down design, differetn testbench
13 Substractor 11_half_substractor, 12_full_substractor
14 Multiplier 13_multiplier This is a high level behavioral modeling example
15 Random Access Memory 14_memory creating memory
16 CAN bus protocol
17 GPIO multiplier
18 Voltage regulator

Advanced development projects

  • Coffee machine
  • Candy machine dispenser
  • SoC
  • Microprocessor/Microcontroller
  • Digital and analog signal processor
  • Graphics processor
  • Neural processor
  • Nvidia type - GPU
  • Neuromorphic processor
  • Mixed signal IC

Resources

Learning to design

  1. Book: Sumir Palnitkar, VLSI Design
  2. Tutorials point
  3. eSim tutorial
  4. Zero to ASIC
  5. VLSI design testing
  6. iverilog

Design online resources

  1. Module definitions given in here
  2. Github repositories for washing machine in here
  3. OpenRAM OpenRAM Github link
  4. Github list of all VLSI System Design IP
  5. Mixed Signal SoC design marathon
  6. Mixed Signal Circuit Design and Simulation
  7. Circuit Design and Simulation
  8. VerificationGuide wesite

Open PDK, EDA and important resource

  1. Google Open Source EDA tools
  2. VSD FLOW by Kunal Ghosh
  3. Free PDK
  4. VLSI and ASIC Technology
  5. FOSSEE Free/Libre and Open Source Software for Education
  6. eSim EDA tool
  7. DIY chip
  8. chipignite - resources
  9. GTKWave
  10. OpenFPGA
  11. Opencores IP

R. Timothy Edwards's OpenCircuitDesign.com

A single point for the suite of open-source Electronic Design Automation tools including Magic, qflow, Netgen, IRSIM, PCB and XCircuit.

  1. Get efabless account for free.
  2. Main website - opencircuitdesign
  3. Open_pdks
  4. Magic VLSI Layout tool
  5. His github repos

Caravel, Efabless expedition

  1. Youtube channel
  2. Caravel user project
  3. Caravel Analog projects
  4. Caravel user projects doc
  5. Caravel

Important resources

  1. VSDOPEN 2022 conference
  2. VSDOpen
  3. RISC-V DIR-V
  4. Redwood
  5. warp-v.com
  6. makerchip

eSim

  1. eSim brochure

  2. FOSSEE Free/Libre and Open Source Software for Education

  3. eSim EDA tool

  4. eSim tutorial

Tsung Wei Huang: OpenTimer

  1. Github link for OpenTimer
  2. Verilog to routing (VTR) VTR

RISC V

  1. RISC V ISA Simulator
  2. pkgs.orgs

-- [India Semiconductor Mission](https://ism.gov.in/)

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