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Add initial support for Olimex iCE40HX8K-EVB #24

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Forty-Bot
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This code currently builds but does not work on real hardware. I have had best results with PNR=nextpnr and PNRFLAGS=--opt-timing. Clock frequencies listed in config.vh are based on timing results from PNR, not from empirical testing. I have been unable to get any output over serial, even with the clock frequency well below timing requirements. I have also tried swapping the TX and RX ports. Please let me know if you have any suggestions for things to try.

Builds but does not work on actual hardware. Perhaps due to something
with the bram?
Generated files should be kept out of source control (unless they are
lengthy or difficult to create).
These are necessary when building with a toolchain that supports both
riscv32 and riscv64.
@samsoniuk
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wow! thank you for the contribution! I have some suggestions in order to try make the darkriscv work in the iCE40HX8K:

  • ensure that the CLK is working (with a counter in order to blink a led with 1Hz)
  • ensure that the RES is working (the RES signal is active high)

As long you ensure that the CLK and RES are present, maybe is possible check about the UART.

The following change will make the UART print the character 'A' regardless the core is working or not (in fact, case the core is running, it will be locked in the putchar function, as long the UART is busy printing 'A'):

index fe63ff6..67bdb31 100644
--- a/rtl/darkuart.v
+++ b/rtl/darkuart.v
@@ -96,8 +96,8 @@ module darkuart
     reg         UART_IREQ  = 0;     // UART interrupt req
     reg         UART_IACK  = 0;     // UART interrupt ack
 
-    reg [ 7:0]  UART_XFIFO = 0;     // UART TX FIFO
-    reg         UART_XREQ  = 0;     // xmit request (core side)
+    reg [ 7:0]  UART_XFIFO = "A";     // UART TX FIFO
+    reg         UART_XREQ  = 1;     // xmit request (core side)
     reg         UART_XACK  = 0;     // xmit ack (uart side)
     reg [15:0]  UART_XBAUD = 0;    // baud rate counter
     reg [ 3:0]  UART_XSTATE= 0;     // idle state
@@ -124,7 +124,7 @@ module darkuart
         begin
             if(BE[1])
             begin
-                UART_XFIFO <= DATAI[15:8];
+                UART_XFIFO <= "B"; // DATAI[15:8];
 `ifdef SIMULATION
                 // print the UART output to console! :)
                 if(DATAI[15:8]!=13) // remove the '\r'
@@ -144,7 +144,7 @@ module darkuart
                     $finish();
                 end
 `else
-                UART_XREQ <= !UART_XACK;    // activate UART!
+                //UART_XREQ <= !UART_XACK;    // activate UART!
 `endif
             end
             //if(BE[2]) UART_TIMER[ 7:0] <= DATAI[23:16];
@@ -179,7 +179,7 @@ module darkuart
                             UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ^UART_XACK) :
                                                             UART_XSTATE+(UART_XBAUD==0);
                                                            
-        UART_XACK   <= RES||UART_XSTATE==`UART_STATE_ACK  ? UART_XREQ : UART_XACK;
+        //UART_XACK   <= RES||UART_XSTATE==`UART_STATE_ACK  ? UART_XREQ : UART_XACK;
     end
 
     assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;

Of course, the simulation will not work with this change (the simulation does not really foreseen the UART printing at 115200 bps in order to run faster).

@samsoniuk
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Another interesting suggestion is loopback the RX and TX in the FPGA to make sure that the UART is correct wired. A small project to test the clock generator to blink a LED at the rate of 1Hz, the reset wired to another LED and loopback the TX/RX may help make sure that the top level is correct wired, clocked and out of reset.

Of course, although the darkriscv worked fine with a small set of different tools (Xilinx ISE, Xilinx Vivado, Icarus Verilog and some reports about Multisim), there is the possibility that the code does not work well with a different set of tools due to syntax tricks that are optimized to infer the correct logic in Xilinx tools.

In fact, I am very curious about the synthesis results from Yosis: how many LUTs are required in the synthesis? how about the maximum frequency?

@Forty-Bot
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Forty-Bot commented Dec 8, 2019

  • ensure that the CLK is working (with a counter in order to blink a led with 1Hz)

This works fine.

ensure that the RES is working (the RES signal is active high)

I'm not so sure how I can check this.

The following change will make the UART print the character 'A' regardless the core is working or not

I do get an A character, but it comes very slowly (once every few seconds, but occasionally many at once).

In fact, I am very curious about the synthesis results from Yosis: how many LUTs are required in the synthesis? how about the maximum frequency?

Here is the output of nextpnr when built with __3STAGE__ only. The __MAC16X16__ option takes up a lot of LUTs. Threading does as well, but not as many. The critical path is delayed due to arithmetic; you might be able to get faster frequency by adding another clock to ALU instructions.

Info: Importing module darksocv
Info: Rule checker, verifying imported design
Info: Checksum: 0x2b69ba0f

Info: constrained 'XCLK' to bel 'X0/Y16/io1'
Info: constrained 'XRES' to bel 'X29/Y0/io0'
Info: constrained 'LED[3]' to bel 'X0/Y31/io1'
Info: constrained 'LED[2]' to bel 'X0/Y31/io0'
Info: constrained 'LED[1]' to bel 'X28/Y0/io0'
Info: constrained 'LED[0]' to bel 'X27/Y0/io1'
Info: constrained 'UART_RXD' to bel 'X26/Y0/io1'
Info: constrained 'UART_TXD' to bel 'X27/Y0/io0'
Info: constrained 'DEBUG[3]' to bel 'X33/Y2/io1'
Info: constrained 'DEBUG[2]' to bel 'X33/Y2/io0'
Info: constrained 'DEBUG[1]' to bel 'X33/Y1/io1'
Info: constrained 'DEBUG[0]' to bel 'X33/Y1/io0'

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info:     1578 LCs used as LUT4 only
Info:      276 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:      208 LCs used as DFF only
Info: Packing carries..
Info:      130 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'SB_PLL40_CORE_inst' to X16/Y0/pll_3
Info: Packing special functions..
Info:   PLL 'SB_PLL40_CORE_inst' has LOCK output, need to pass all outputs via LUT
Info:   LUT strategy for LOCK: move all users to new LUT
Info:   constrained 'SB_PLL40_CORE_inst_PLL$nextpnr_LOCK_lut_through' to X1/Y1/lc0
Info: Promoting globals..
Info: promoting CLK (fanout 508)
Info: promoting DRES[7] [reset] (fanout 106)
Info: promoting $abc$21288$auto$dff2dffe.cc:158:make_patterns_logic$17538 [reset] (fanout 33)
Info: promoting $abc$21288$auto$rtlil.cc:1969:NotGate$21202 [reset] (fanout 24)
Info: promoting $abc$21288$auto$rtlil.cc:1969:NotGate$21134 [reset] (fanout 20)
Info: promoting $abc$21288$auto$dff2dffe.cc:158:make_patterns_logic$17523 [cen] (fanout 145)
Info: promoting $abc$21288$auto$dff2dffe.cc:158:make_patterns_logic$19828 [cen] (fanout 32)
Info: promoting $abc$21288$auto$dff2dffe.cc:158:make_patterns_logic$18009 [cen] (fanout 32)
Info: Constraining chains...
Info:       15 LCs used to legalise carry chains.
Info: Checksum: 0xdf4833fc

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x08310469

Info: Device utilisation:
Info: 	         ICESTORM_LC:  2210/ 7680    28%
Info: 	        ICESTORM_RAM:    20/   32    62%
Info: 	               SB_IO:    12/  256     4%
Info: 	               SB_GB:     8/    8   100%
Info: 	        ICESTORM_PLL:     1/    2    50%
Info: 	         SB_WARMBOOT:     0/    1     0%

Info: Placed 14 cells based on constraints.
Info: Creating initial analytic placement for 1832 cells, random placement wirelen = 62515.
Info:     at initial placer iter 0, wirelen = 1209
Info:     at initial placer iter 1, wirelen = 1270
Info:     at initial placer iter 2, wirelen = 1206
Info:     at initial placer iter 3, wirelen = 1222
Info: Running main analytical placer.
Info:     at iteration #1, type ALL: wirelen solved = 1207, spread = 16168, legal = 17731; time = 0.04s
Info:     at iteration #2, type ALL: wirelen solved = 1351, spread = 13600, legal = 15857; time = 0.04s
Info:     at iteration #3, type ALL: wirelen solved = 1682, spread = 14136, legal = 15162; time = 0.03s
Info:     at iteration #4, type ALL: wirelen solved = 2033, spread = 14737, legal = 16126; time = 0.04s
Info:     at iteration #5, type ALL: wirelen solved = 2284, spread = 14250, legal = 15885; time = 0.07s
Info:     at iteration #6, type ALL: wirelen solved = 2698, spread = 13671, legal = 15597; time = 0.03s
Info:     at iteration #7, type ALL: wirelen solved = 2896, spread = 13991, legal = 16373; time = 0.04s
Info:     at iteration #8, type ALL: wirelen solved = 3268, spread = 14485, legal = 15795; time = 0.04s
Info: HeAP Placer Time: 0.49s
Info:   of which solving equations: 0.28s
Info:   of which spreading cells: 0.02s
Info:   of which strict legalisation: 0.11s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 569, wirelen = 15162
Info:   at iteration #5: temp = 0.000000, timing cost = 580, wirelen = 11918
Info:   at iteration #10: temp = 0.000000, timing cost = 509, wirelen = 11358
Info:   at iteration #15: temp = 0.000000, timing cost = 504, wirelen = 11060
Info:   at iteration #20: temp = 0.000000, timing cost = 473, wirelen = 10821
Info:   at iteration #21: temp = 0.000000, timing cost = 481, wirelen = 10783 
Info: SA placement time 1.02s

Info: Max frequency for clock 'XCLK$SB_IO_IN': 195.81 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock  'CLK_$glb_clk': 42.47 MHz (PASS at 12.00 MHz)

Info: Max delay <async>              -> posedge CLK_$glb_clk : 1.68 ns
Info: Max delay <async>              -> posedge XCLK$SB_IO_IN: 3.70 ns
Info: Max delay posedge CLK_$glb_clk -> <async>              : 6.45 ns

Info: Slack histogram:
Info:  legend: * represents 3 endpoint(s)
Info:          + represents [1,3) endpoint(s)
Info: [ 59787,  60908) |*****+
Info: [ 60908,  62029) |***+
Info: [ 62029,  63150) |*******+
Info: [ 63150,  64271) |***+
Info: [ 64271,  65392) |****+
Info: [ 65392,  66513) |*********+
Info: [ 66513,  67634) |********+
Info: [ 67634,  68755) |***********+
Info: [ 68755,  69876) |*************+
Info: [ 69876,  70997) |***************************+
Info: [ 70997,  72118) |****************************************+
Info: [ 72118,  73239) |*****************************+
Info: [ 73239,  74360) |*******************************************+
Info: [ 74360,  75481) |************************************************************ 
Info: [ 75481,  76602) |****************************************+
Info: [ 76602,  77723) |****************************** 
Info: [ 77723,  78844) |*********************+
Info: [ 78844,  79965) |*********************************************************+
Info: [ 79965,  81086) |********************************************+
Info: [ 81086,  82207) |****************************************************+
Info: Checksum: 0xf6ea04f6

Info: Routing..
Info: Setting up routing queue.
Info: Routing 7725 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs
Info:       1000 |       47        952 |   47   952 |      6789
Info:       2000 |       87       1912 |   40   960 |      5843
Info:       3000 |      148       2851 |   61   939 |      4916
Info:       4000 |      329       3670 |  181   819 |      4150
Info:       5000 |      521       4478 |  192   808 |      3397
Info:       6000 |      755       5244 |  234   766 |      2745
Info:       7000 |     1040       5959 |  285   715 |      2134
Info:       8000 |     1325       6674 |  285   715 |      1536
Info:       9000 |     1684       7315 |  359   641 |      1112
Info:      10000 |     2128       7871 |  444   556 |       904
Info:      11000 |     2580       8419 |  452   548 |       659
Info:      11902 |     2745       9157 |  165   738 |         0
Info: Routing complete.
Info: Route time 2.40s
Info: Checksum: 0x5c8e3b5b

Info: Critical path report for clock 'XCLK$SB_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source $abc$21288$auto$blifparse.cc:492:parse_blif$21300_LC.O
Info:  0.6  1.1    Net $abc$21288$auto$ice40_ffinit.cc:141:execute$21072 budget 26.226999 ns (9,1) -> (9,1)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22645_LC.I0
Info:  0.4  1.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22645_LC.O
Info:  0.9  2.5    Net IRES[0] budget 26.128000 ns (9,1) -> (7,1)
Info:                Sink $nextpnr_ICESTORM_LC_1.I1
Info:  0.3  2.7  Source $nextpnr_ICESTORM_LC_1.COUT
Info:  0.0  2.7    Net $nextpnr_ICESTORM_LC_1$O budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[1].carry$CARRY.CIN
Info:  0.1  2.9  Source $auto$alumacc.cc:474:replace_alu$10023.slice[1].carry$CARRY.COUT
Info:  0.0  2.9    Net $auto$alumacc.cc:474:replace_alu$10023.C[2] budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[2].adder_LC.CIN
Info:  0.1  3.0  Source $auto$alumacc.cc:474:replace_alu$10023.slice[2].adder_LC.COUT
Info:  0.0  3.0    Net $auto$alumacc.cc:474:replace_alu$10023.C[3] budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[3].adder_LC.CIN
Info:  0.1  3.1  Source $auto$alumacc.cc:474:replace_alu$10023.slice[3].adder_LC.COUT
Info:  0.0  3.1    Net $auto$alumacc.cc:474:replace_alu$10023.C[4] budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[4].adder_LC.CIN
Info:  0.1  3.2  Source $auto$alumacc.cc:474:replace_alu$10023.slice[4].adder_LC.COUT
Info:  0.0  3.2    Net $auto$alumacc.cc:474:replace_alu$10023.C[5] budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[5].adder_LC.CIN
Info:  0.1  3.4  Source $auto$alumacc.cc:474:replace_alu$10023.slice[5].adder_LC.COUT
Info:  0.0  3.4    Net $auto$alumacc.cc:474:replace_alu$10023.C[6] budget 0.000000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[6].adder_LC.CIN
Info:  0.1  3.5  Source $auto$alumacc.cc:474:replace_alu$10023.slice[6].adder_LC.COUT
Info:  0.3  3.8    Net $auto$alumacc.cc:474:replace_alu$10023.C[7] budget 0.260000 ns (7,1) -> (7,1)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10023.slice[7].adder_LC.I3
Info:  0.3  4.1  Source $auto$alumacc.cc:474:replace_alu$10023.slice[7].adder_LC.O
Info:  0.6  4.7    Net $abc$21288$auto$wreduce.cc:455:run$9896[7] budget 26.474001 ns (7,1) -> (7,2)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$21307_LC.I0
Info:  0.5  5.1  Setup $abc$21288$auto$blifparse.cc:492:parse_blif$21307_LC.I0
Info: 2.8 ns logic, 2.3 ns routing

Info: Critical path report for clock 'CLK_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  2.1  2.1  Source core0.REG1.0.0.0_RAM.RDATA_0
Info:  1.6  3.7    Net $abc$21288$auto$memory_bram.cc:922:replace_cell$10121[0] budget 0.000000 ns (8,13) -> (13,13)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$21371_LC.I0
Info:  0.4  4.2  Source $abc$21288$auto$blifparse.cc:492:parse_blif$21371_LC.O
Info:  1.6  5.8    Net core0.S1REG[0] budget 5.865000 ns (13,13) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[0].carry$CARRY.I1
Info:  0.3  6.0  Source $auto$alumacc.cc:474:replace_alu$10057.slice[0].carry$CARRY.COUT
Info:  0.0  6.0    Net $auto$alumacc.cc:474:replace_alu$10057.C[1] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[1].adder_LC.CIN
Info:  0.1  6.1  Source $auto$alumacc.cc:474:replace_alu$10057.slice[1].adder_LC.COUT
Info:  0.0  6.1    Net $auto$alumacc.cc:474:replace_alu$10057.C[2] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[2].adder_LC.CIN
Info:  0.1  6.3  Source $auto$alumacc.cc:474:replace_alu$10057.slice[2].adder_LC.COUT
Info:  0.0  6.3    Net $auto$alumacc.cc:474:replace_alu$10057.C[3] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[3].adder_LC.CIN
Info:  0.1  6.4  Source $auto$alumacc.cc:474:replace_alu$10057.slice[3].adder_LC.COUT
Info:  0.0  6.4    Net $auto$alumacc.cc:474:replace_alu$10057.C[4] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[4].adder_LC.CIN
Info:  0.1  6.5  Source $auto$alumacc.cc:474:replace_alu$10057.slice[4].adder_LC.COUT
Info:  0.0  6.5    Net $auto$alumacc.cc:474:replace_alu$10057.C[5] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[5].adder_LC.CIN
Info:  0.1  6.6  Source $auto$alumacc.cc:474:replace_alu$10057.slice[5].adder_LC.COUT
Info:  0.0  6.6    Net $auto$alumacc.cc:474:replace_alu$10057.C[6] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[6].adder_LC.CIN
Info:  0.1  6.8  Source $auto$alumacc.cc:474:replace_alu$10057.slice[6].adder_LC.COUT
Info:  0.0  6.8    Net $auto$alumacc.cc:474:replace_alu$10057.C[7] budget 0.000000 ns (12,7) -> (12,7)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[7].adder_LC.CIN
Info:  0.1  6.9  Source $auto$alumacc.cc:474:replace_alu$10057.slice[7].adder_LC.COUT
Info:  0.2  7.1    Net $auto$alumacc.cc:474:replace_alu$10057.C[8] budget 0.190000 ns (12,7) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[8].adder_LC.CIN
Info:  0.1  7.2  Source $auto$alumacc.cc:474:replace_alu$10057.slice[8].adder_LC.COUT
Info:  0.0  7.2    Net $auto$alumacc.cc:474:replace_alu$10057.C[9] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[9].adder_LC.CIN
Info:  0.1  7.3  Source $auto$alumacc.cc:474:replace_alu$10057.slice[9].adder_LC.COUT
Info:  0.0  7.3    Net $auto$alumacc.cc:474:replace_alu$10057.C[10] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[10].adder_LC.CIN
Info:  0.1  7.5  Source $auto$alumacc.cc:474:replace_alu$10057.slice[10].adder_LC.COUT
Info:  0.0  7.5    Net $auto$alumacc.cc:474:replace_alu$10057.C[11] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[11].adder_LC.CIN
Info:  0.1  7.6  Source $auto$alumacc.cc:474:replace_alu$10057.slice[11].adder_LC.COUT
Info:  0.0  7.6    Net $auto$alumacc.cc:474:replace_alu$10057.C[12] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[12].carry$CARRY.CIN
Info:  0.1  7.7  Source $auto$alumacc.cc:474:replace_alu$10057.slice[12].carry$CARRY.COUT
Info:  0.0  7.7    Net $auto$alumacc.cc:474:replace_alu$10057.C[13] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[13].carry$CARRY.CIN
Info:  0.1  7.9  Source $auto$alumacc.cc:474:replace_alu$10057.slice[13].carry$CARRY.COUT
Info:  0.0  7.9    Net $auto$alumacc.cc:474:replace_alu$10057.C[14] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[14].carry$CARRY.CIN
Info:  0.1  8.0  Source $auto$alumacc.cc:474:replace_alu$10057.slice[14].carry$CARRY.COUT
Info:  0.0  8.0    Net $auto$alumacc.cc:474:replace_alu$10057.C[15] budget 0.000000 ns (12,8) -> (12,8)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[15].carry$CARRY.CIN
Info:  0.1  8.1  Source $auto$alumacc.cc:474:replace_alu$10057.slice[15].carry$CARRY.COUT
Info:  0.2  8.3    Net $auto$alumacc.cc:474:replace_alu$10057.C[16] budget 0.190000 ns (12,8) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[16].carry$CARRY.CIN
Info:  0.1  8.4  Source $auto$alumacc.cc:474:replace_alu$10057.slice[16].carry$CARRY.COUT
Info:  0.0  8.4    Net $auto$alumacc.cc:474:replace_alu$10057.C[17] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[17].carry$CARRY.CIN
Info:  0.1  8.6  Source $auto$alumacc.cc:474:replace_alu$10057.slice[17].carry$CARRY.COUT
Info:  0.0  8.6    Net $auto$alumacc.cc:474:replace_alu$10057.C[18] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[18].carry$CARRY.CIN
Info:  0.1  8.7  Source $auto$alumacc.cc:474:replace_alu$10057.slice[18].carry$CARRY.COUT
Info:  0.0  8.7    Net $auto$alumacc.cc:474:replace_alu$10057.C[19] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[19].carry$CARRY.CIN
Info:  0.1  8.8  Source $auto$alumacc.cc:474:replace_alu$10057.slice[19].carry$CARRY.COUT
Info:  0.0  8.8    Net $auto$alumacc.cc:474:replace_alu$10057.C[20] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[20].carry$CARRY.CIN
Info:  0.1  8.9  Source $auto$alumacc.cc:474:replace_alu$10057.slice[20].carry$CARRY.COUT
Info:  0.0  8.9    Net $auto$alumacc.cc:474:replace_alu$10057.C[21] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[21].carry$CARRY.CIN
Info:  0.1  9.1  Source $auto$alumacc.cc:474:replace_alu$10057.slice[21].carry$CARRY.COUT
Info:  0.0  9.1    Net $auto$alumacc.cc:474:replace_alu$10057.C[22] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[22].carry$CARRY.CIN
Info:  0.1  9.2  Source $auto$alumacc.cc:474:replace_alu$10057.slice[22].carry$CARRY.COUT
Info:  0.0  9.2    Net $auto$alumacc.cc:474:replace_alu$10057.C[23] budget 0.000000 ns (12,9) -> (12,9)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[23].carry$CARRY.CIN
Info:  0.1  9.3  Source $auto$alumacc.cc:474:replace_alu$10057.slice[23].carry$CARRY.COUT
Info:  0.2  9.5    Net $auto$alumacc.cc:474:replace_alu$10057.C[24] budget 0.190000 ns (12,9) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[24].carry$CARRY.CIN
Info:  0.1  9.6  Source $auto$alumacc.cc:474:replace_alu$10057.slice[24].carry$CARRY.COUT
Info:  0.0  9.6    Net $auto$alumacc.cc:474:replace_alu$10057.C[25] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[25].carry$CARRY.CIN
Info:  0.1  9.8  Source $auto$alumacc.cc:474:replace_alu$10057.slice[25].carry$CARRY.COUT
Info:  0.0  9.8    Net $auto$alumacc.cc:474:replace_alu$10057.C[26] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[26].carry$CARRY.CIN
Info:  0.1  9.9  Source $auto$alumacc.cc:474:replace_alu$10057.slice[26].carry$CARRY.COUT
Info:  0.0  9.9    Net $auto$alumacc.cc:474:replace_alu$10057.C[27] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[27].carry$CARRY.CIN
Info:  0.1 10.0  Source $auto$alumacc.cc:474:replace_alu$10057.slice[27].carry$CARRY.COUT
Info:  0.0 10.0    Net $auto$alumacc.cc:474:replace_alu$10057.C[28] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[28].carry$CARRY.CIN
Info:  0.1 10.1  Source $auto$alumacc.cc:474:replace_alu$10057.slice[28].carry$CARRY.COUT
Info:  0.0 10.1    Net $auto$alumacc.cc:474:replace_alu$10057.C[29] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[29].carry$CARRY.CIN
Info:  0.1 10.3  Source $auto$alumacc.cc:474:replace_alu$10057.slice[29].carry$CARRY.COUT
Info:  0.0 10.3    Net $auto$alumacc.cc:474:replace_alu$10057.C[30] budget 0.000000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[30].carry$CARRY.CIN
Info:  0.1 10.4  Source $auto$alumacc.cc:474:replace_alu$10057.slice[30].carry$CARRY.COUT
Info:  0.3 10.6    Net $auto$alumacc.cc:474:replace_alu$10057.C[31] budget 0.260000 ns (12,10) -> (12,10)
Info:                Sink $auto$alumacc.cc:474:replace_alu$10057.slice[31].adder_LC.I3
Info:  0.3 11.0  Source $auto$alumacc.cc:474:replace_alu$10057.slice[31].adder_LC.O
Info:  1.3 12.3    Net DADDR[31] budget 5.861000 ns (12,10) -> (12,16)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22027_LC.I2
Info:  0.4 12.7  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22027_LC.O
Info:  0.6 13.3    Net $abc$21288$core0.DATAI[23]_inv budget 5.142000 ns (12,16) -> (12,16)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22741_LC.I0
Info:  0.4 13.7  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22741_LC.O
Info:  0.6 14.3    Net $abc$21288$n3115 budget 4.850000 ns (12,16) -> (12,16)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22742_LC.I3
Info:  0.3 14.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22742_LC.O
Info:  0.6 15.2    Net $abc$21288$techmap\core0.$ternary$../rtl/darkriscv.v:277$9425_Y[7]_inv budget 5.206000 ns (12,16) -> (13,15)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22050_LC.I1
Info:  0.4 15.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22050_LC.O
Info:  1.6 17.2    Net $abc$21288$n2297 budget 5.474000 ns (13,15) -> (16,10)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22196_LC.I1
Info:  0.4 17.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22196_LC.O
Info:  0.6 18.2    Net $abc$21288$n2496 budget 4.933000 ns (16,10) -> (17,10)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22457_LC.I2
Info:  0.4 18.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22457_LC.O
Info:  1.6 20.2    Net $abc$21288$n2824 budget 5.318000 ns (17,10) -> (21,6)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22444_LC.I3
Info:  0.3 20.5  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22444_LC.O
Info:  0.6 21.1    Net $abc$21288$techmap\core0.$ternary$../rtl/darkriscv.v:410$9532_Y[31] budget 5.238000 ns (21,6) -> (21,5)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22443_LC.I0
Info:  0.4 21.5  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22443_LC.O
Info:  0.6 22.1    Net $abc$21288$n2810 budget 5.174000 ns (21,5) -> (22,5)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22463_LC.I0
Info:  0.4 22.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22463_LC.O
Info:  1.3 23.9    Net $abc$21288$auto$memory_bram.cc:833:replace_cell$10161[15] budget 6.063000 ns (22,5) -> (25,7)
Info:                Sink core0.REG2.1.0.0_RAM.WDATA_15
Info:  0.1 24.0  Setup core0.REG2.1.0.0_RAM.WDATA_15
Info: 10.6 ns logic, 13.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge CLK_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source UART_RXD$sb_io.D_IN_0
Info:  1.3  1.3    Net UART_RXD$SB_IO_IN budget 82.864998 ns (26,0) -> (24,1)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22637_LC.I0
Info:  0.5  1.7  Setup $abc$21288$auto$blifparse.cc:492:parse_blif$22637_LC.I0
Info: 0.5 ns logic, 1.3 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge XCLK$SB_IO_IN':
Info: curr total
Info:  0.0  0.0  Source XRES$sb_io.D_IN_0
Info:  2.2  2.2    Net XRES$SB_IO_IN budget 41.428001 ns (29,0) -> (6,1)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$21556_LC.I2
Info:  0.4  2.6  Source $abc$21288$auto$blifparse.cc:492:parse_blif$21556_LC.O
Info:  1.6  4.2    Net $abc$21288$auto$dff2dffe.cc:158:make_patterns_logic$18952 budget 40.303001 ns (6,1) -> (6,2)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$21301_LC.CEN
Info:  0.1  4.3  Setup $abc$21288$auto$blifparse.cc:492:parse_blif$21301_LC.CEN
Info: 0.5 ns logic, 3.8 ns routing

Info: Critical path report for cross-domain path 'posedge CLK_$glb_clk' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22573_LC.O
Info:  1.0  1.5    Net uart0.UART_XSTATE[1] budget 15.890000 ns (23,1) -> (22,3)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22841_LC.I3
Info:  0.3  1.8  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22841_LC.O
Info:  0.6  2.4    Net $abc$21288$n3215 budget 15.711000 ns (22,3) -> (22,2)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22843_LC.I2
Info:  0.4  2.8  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22843_LC.O
Info:  0.6  3.4    Net $abc$21288$n3217 budget 15.711000 ns (22,2) -> (22,1)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22844_LC.I0
Info:  0.4  3.8  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22844_LC.O
Info:  0.6  4.4    Net $abc$21288$n3218 budget 15.711000 ns (22,1) -> (22,1)
Info:                Sink $abc$21288$auto$blifparse.cc:492:parse_blif$22845_LC.I2
Info:  0.4  4.8  Source $abc$21288$auto$blifparse.cc:492:parse_blif$22845_LC.O
Info:  1.6  6.4    Net UART_TXD$SB_IO_OUT budget 15.979000 ns (22,1) -> (27,0)
Info:                Sink UART_TXD$sb_io.D_OUT_0
Info: 2.1 ns logic, 4.3 ns routing

Info: Max frequency for clock 'XCLK$SB_IO_IN': 195.16 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock  'CLK_$glb_clk': 41.75 MHz (PASS at 12.00 MHz)

Info: Max delay <async>              -> posedge CLK_$glb_clk : 1.75 ns
Info: Max delay <async>              -> posedge XCLK$SB_IO_IN: 4.30 ns
Info: Max delay posedge CLK_$glb_clk -> <async>              : 6.37 ns

Info: Slack histogram:
Info:  legend: * represents 5 endpoint(s)
Info:          + represents [1,5) endpoint(s)
Info: [ 59379,  60521) |****+
Info: [ 60521,  61663) |***+
Info: [ 61663,  62805) |*****+
Info: [ 62805,  63947) |***+
Info: [ 63947,  65089) |*+
Info: [ 65089,  66231) |*+
Info: [ 66231,  67373) |*************+
Info: [ 67373,  68515) |**********+
Info: [ 68515,  69657) |**+
Info: [ 69657,  70799) |********+
Info: [ 70799,  71941) |****************+
Info: [ 71941,  73083) |************************+
Info: [ 73083,  74225) |************************************************************ 
Info: [ 74225,  75367) |*************************************+
Info: [ 75367,  76509) |**************+
Info: [ 76509,  77651) |***************+
Info: [ 77651,  78793) |********************************************+
Info: [ 78793,  79935) |*****************************************+
Info: [ 79935,  81077) |****************************+
Info: [ 81077,  82219) |***************************************+

@samsoniuk
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samsoniuk commented Dec 9, 2019

This is a good news, because the 'A' in the output means that the clock is working as expected, since the UART is working with the correct baud rate, and that the reset is working as expected, since the UART state machine uses the RES signal. As long there are no '\n' in the stream, the terminal is probably buffering the 'A' stream, but this is observable in the Icarus simulation too.

About the synthesis output, I guess the synthesis requires 2210LUTs and it appears to be very consistent with the RV32E in the Spartan-3E, which takes about 1800LUTs without threading. The MAC instruction uses a special DSP48 block in the Xilinx FPGAs, but it is not mandatory and can be disabled for sure. The threading requires more LUTs, in a way that the RV32E without threading appears to fit better in FPGAs w/ LUT4 technology.

As long the clock, reset and UART appears to work well, another suggestion in order to debug the design is double-check about the ROM and RAM loading. In the case of Xilinx tools there are lots of messages regarding the ROM and RAM loading, in a way that sometimes the memories are not correctly loaded. Case the ROM and RAM are correctly loaded, maybe test w/ the 2-stage pipeline version is a good thing, as long the memories are wired in a different way.

One interesting way to debug the ROM content is create some comparators with the IDATA and IADDR to trigger some LEDs when specific patterns are detected. For example, as long the first instruction in the ROM is 0x00001737 and the second is 0x00472783, it is possible compare the IDATA and activate separate LEDs regarding that instructions, something like this:

reg [3:0] LED = 0;

always@(posedge CLK)
begin
    if(IDATA== 0x00001737) LED[0] <= 1;
    if(IDATA== 0x00472783) LED[1] <= 1;
    ...
end

Case the LEDs never activate, for sure there is something wrong with the ROM. In the case of Xilinx tools, the ROM is typically inferred as a synchronous BlockRAM with registered output, but I am not sure about the behaviour of tools from other manufacturers.

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2 participants