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Fix some IntelliJ warnings #1365

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Nov 7, 2023
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Original file line number Diff line number Diff line change
Expand Up @@ -82,14 +82,11 @@ public int analyzePacket(Packet packet, StringBuilder brief,
int tf = (packet.get(0) >> 3) & 0x03;
boolean nhc = (packet.get(0) & SICSLOWPAN_IPHC_NH_C) > 0;
int hlim = (packet.get(0) & 0x03);
switch (hlim) {
case 0x02:
hlim = 64;
break;
case 0x03:
hlim = 255;
break;
}
hlim = switch (hlim) {
case 0x02 -> 64;
case 0x03 -> 255;
default -> hlim;
};
int cid = (packet.get(1) >> 7) & 0x01;
int sac = (packet.get(1) >> 6) & 0x01;
int sam = (packet.get(1) >> 4) & 0x03;
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45 changes: 22 additions & 23 deletions java/se/sics/mspsim/core/Multiplier.java
Original file line number Diff line number Diff line change
Expand Up @@ -78,30 +78,29 @@ public Multiplier(MSP430Core cpu, int[] memory, int offset) {

@Override
public int read(int address, boolean word, long cycles) {
switch (address) {
case MPY:
return mpy;
case MPYS:
return mpys;
case MAC:
return mac;
case MACS:
return macs;
case OP2:
return op2;
case RESHI:
if (DEBUG) log("read res hi: " + resHi );
return resHi;
case RESLO:
if (DEBUG) log("read res lo: " + resLo );
return resLo;
case SUMEXT:
if (DEBUG) log("read sumext: " + sumext);
return sumext;
default:
return switch (address) {
case MPY -> mpy;
case MPYS -> mpys;
case MAC -> mac;
case MACS -> macs;
case OP2 -> op2;
case RESHI -> {
if (DEBUG) log("read res hi: " + resHi);
yield resHi;
}
case RESLO -> {
if (DEBUG) log("read res lo: " + resLo);
yield resLo;
}
case SUMEXT -> {
if (DEBUG) log("read sumext: " + sumext);
yield sumext;
}
default -> {
logw(WarningType.EMULATION_ERROR, "read unhandled address: 0x" + Utils.hex(address, 4));
return 0;
}
yield 0;
}
};
}

@Override
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90 changes: 37 additions & 53 deletions java/se/sics/mspsim/core/Multiplier32.java
Original file line number Diff line number Diff line change
Expand Up @@ -109,60 +109,44 @@ public Multiplier32(MSP430Core cpu, int[] memory, int offset) {
@Override
public int read(int address, boolean word, long cycles) {
address = address - offset;
switch (address) {
case MPY:
return mpy;
case MPYS:
return mpys;
case MAC:
return mac;
case MACS:
return macs;
case OP2:
return op2;
case RESHI:
if (DEBUG) log("read res hi: " + resHi );
return resHi;
case RESLO:
if (DEBUG) log("read res lo: " + resLo );
return resLo;
case SUMEXT:
if (DEBUG) log("read sumext: " + sumext);
return sumext;
case MPY32L:
return mpy32L;
case MPY32H:
return mpy32H;
case MPYS32L:
return mpys32L;
case MPYS32H:
return mpys32H;
case MAC32L:
return mac32L;
case MAC32H:
return mac32H;
case MACS32L:
return macs32L;
case MACS32H:
return macs32H;
case OP2L:
return op2L;
case OP2H:
return op2H;
case RES0:
return res0;
case RES1:
return res1;
case RES2:
return res2;
case RES3:
return res3;
case MPY32CTL0:
return mpy32ctl0;
default:
logw(WarningType.EMULATION_ERROR, "read unhandled address: 0x" + Utils.hex(address, 4));
return 0;
return switch (address) {
case MPY -> mpy;
case MPYS -> mpys;
case MAC -> mac;
case MACS -> macs;
case OP2 -> op2;
case RESHI -> {
if (DEBUG) log("read res hi: " + resHi);
yield resHi;
}
case RESLO -> {
if (DEBUG) log("read res lo: " + resLo);
yield resLo;
}
case SUMEXT -> {
if (DEBUG) log("read sumext: " + sumext);
yield sumext;
}
case MPY32L -> mpy32L;
case MPY32H -> mpy32H;
case MPYS32L -> mpys32L;
case MPYS32H -> mpys32H;
case MAC32L -> mac32L;
case MAC32H -> mac32H;
case MACS32L -> macs32L;
case MACS32H -> macs32H;
case OP2L -> op2L;
case OP2H -> op2H;
case RES0 -> res0;
case RES1 -> res1;
case RES2 -> res2;
case RES3 -> res3;
case MPY32CTL0 -> mpy32ctl0;
default -> {
logw(WarningType.EMULATION_ERROR, "read unhandled address: 0x" + Utils.hex(address, 4));
yield 0;
}
};
}

@Override
Expand Down