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hi @iv2nl0b9v the systemverilog plugin has been moved to https://github.com/chipsalliance/synlig repository. Can you check if the issue you're reporting is present there? If, please report this problem there
Repro
UHDM converter doesn't seem to support SV bit vector functions: https://circuitcove.com/system-tasks-vector/
Not sure if it's intended.
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