perf: lane vrf-alu-vrf operations not pipelined

[SharzyL]

From the following waveform (from mill -i tests.run[stripmining-huge.mlir]), it can be observed that when executing vadd.vi v8, v8, 2, vrf write is triggered one time per 5 cycles, which means it only utilized 1/5 bandwidth of vrf and alu. 5 cycles consists of

1. read vrf
2. vrf output
3. save vrf output to reg
4. compute and save result
5. write vrf

They should be pipelined to avoid wasting bandwidth.