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EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator

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PIM EDA Suite

Architecture-level EDA toolchain for processing-in-memory convolutional neural network accelerators.

Introduction

PIM toolchain is suite of open-source tools designed for processing-in-memory architectures running convolutional neural networks. The framework of the toolchain is shown below. framework

The toolchain has three main tools, including an architecture synthesizer, a compiler, and a simulator.

  • The synthesizer (PIMSYN-NN) takes a neural network description (ONNX format) and design constraints as inputs, and generates an architecture instance based on a parameterized architecture template. Design space exploration is performed during the synthesis process to optimize the architecture.

  • The compiler (PIMCOMP-NN) takes the neural network description and the architecture instance as inputs, and generates the instruction sequence together with optimized task mapping and scheduling. The instructions are based on a defined instruction set architecture.

  • The simulator (PIMSIM-NN) takes the architecture and the instruction sequence as inputs, and performs a behavior-level simulation to get the NN inference performance results of the latency, power, energy, etc.

Tools' Links

Compiler (PIMCOMP-NN)

Architecture Synthesizer (PIMSYN-NN)

Simulator (PIMSIM-NN)

Related Publications

[1] Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen, "PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators", in Design Automation Conference (DAC'23), 2023. [Bibtex] [ArXiv]

[2] Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen, "PIMSYN: Synthesizing Processing-in-memory CNN Accelerators", in Design, Automation and Test in Europe Conference (DATE'24), 2024. [Bibtex] [ArXiv]

[3] Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen, "PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators", in Design, Automation and Test in Europe Conference (DATE'24), 2024. [Bibtex] [ArXiv]

[4] Wanqian Li, Yinhe Han, Xiaoming Chen, “Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators”, ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 29, no. 1, pp. 1-24, 2024. [Bibtex]

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EDA toolchain for processing-in-memory architectures, including an architecture synthesizer, a compiler, and a simulator

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