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Harmonica2 verilog generates "wire release;" which causes error in tool chains #12

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ramyadhadidi opened this issue Jun 21, 2016 · 0 comments

ramyadhadidi commented Jun 21, 2016

I think "release" is a keyword in Verilog. Harmonica2 generates a wire with this name and therefore causes an error on Xilinx tool chain

code example:

wire release;
assign release = __x172525;

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