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SRAMs with 0 address bits generate invalid Verilog. #11

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cdkersey opened this issue Jun 8, 2016 · 0 comments
Open

SRAMs with 0 address bits generate invalid Verilog. #11

cdkersey opened this issue Jun 8, 2016 · 0 comments

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@cdkersey
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cdkersey commented Jun 8, 2016

A 1-word synchronous SRAM is essentially a register, but the generated verilog code contains lines like:

wire [18446744073709551615:0] __mem_da1369;

This is bad.
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