A Python package (with examples) that provides a Python wrapper around a SystemVerilog module and builds a complex testbench around it using the Verilator simulator.
git clone https://github.com/bmartini/vpw-testbench.git
cd vpw-testbench
./example.py
The testbench script in combination with the vpw package will take the SystemVerilog RTL files within the 'hdl' directory and creates a pybind11 shared object that is then used by the testbench script to interact with the SystemVerilog module.
Install the package directly from GitHub using the follower command.
pip install git+https://github.com/bmartini/vpw-testbench.git
Or to upgrade an already installed VPW package.
pip install --upgrade --force-reinstall --no-deps git+https://github.com/bmartini/vpw-testbench.git
Add to remove use the standard pip command.
pip uninstall vpw-testbench
The following packages and programs need to be installed to get VPW working.
Besides the default python install the following packages need to be installed.
python3 -m pip install typing parsy pybind11
Download and install the Verilator simulator.
sudo apt-get install -y \
ccache zlib1g autoconf git python3 make g++ ca-certificates \
flex bison libfl2 libfl-dev zlibc zlib1g-dev libgoogle-perftools-dev numactl
git clone https://github.com/verilator/verilator.git
cd verilator
git checkout stable
autoconf
./configure
make -j `nproc`
sudo make install
cd ..
rm -rf verilator
To view the wave forms created by the testbench I recommend GTKWave. The easiest way to install it is via installing Icarus Verilog (iverilog).
git clonce git://github.com/steveicarus/iverilog.git
cd iverilog
sh autoconf.sh
./configure
make
sudo make install
Explanation of use can be found here.