update PIO code for SoC integration

- add duart debug for bare iron testing
- add wait states on FIFO commits for when CPU clock is much
faster than PIO clock.

more wait states will be needed for correct operation in the
future

libs/xous-pio/src/lib.rs

@@ -389,6 +389,20 @@ impl PioSm {
             SmBit::Sm2 => self.pio.wo(rp_pio::SFR_TXF2, data),
             SmBit::Sm3 => self.pio.wo(rp_pio::SFR_TXF3, data),
         }
+        unsafe { // let the write go through before continuing
+            core::arch::asm!(
+                ".word 0x500F",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+                "fence",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+            );
+        }
     }
     pub fn sm_txfifo_push_u16_msb(&mut self, data: u16) {
         match self.sm {
@@ -397,6 +411,20 @@ impl PioSm {
             SmBit::Sm2 => self.pio.wo(rp_pio::SFR_TXF2, (data as u32) << 16),
             SmBit::Sm3 => self.pio.wo(rp_pio::SFR_TXF3, (data as u32) << 16),
         }
+        unsafe { // let the write go through before continuing
+            core::arch::asm!(
+                ".word 0x500F",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+                "fence",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+            );
+        }
     }
     #[allow(dead_code)]
     pub fn sm_txfifo_push_u16_lsb(&mut self, data: u16) {
@@ -406,6 +434,20 @@ impl PioSm {
             SmBit::Sm2 => self.pio.wo(rp_pio::SFR_TXF2, data as u32),
             SmBit::Sm3 => self.pio.wo(rp_pio::SFR_TXF3, data as u32),
         }
+        unsafe { // let the write go through before continuing
+            core::arch::asm!(
+                ".word 0x500F",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+                "fence",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+            );
+        }
     }
     pub fn sm_txfifo_push_u8_msb(&mut self, data: u8) {
         match self.sm {
@@ -414,6 +456,20 @@ impl PioSm {
             SmBit::Sm2 => self.pio.wo(rp_pio::SFR_TXF2, (data as u32) << 24),
             SmBit::Sm3 => self.pio.wo(rp_pio::SFR_TXF3, (data as u32) << 24),
         }
+        unsafe { // let the write go through before continuing
+            core::arch::asm!(
+                ".word 0x500F",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+                "fence",
+                "nop",
+                "nop",
+                "nop",
+                "nop",
+            );
+        }
     }
     pub fn sm_rxfifo_is_empty(&self) -> bool {
         (self.pio.rf(rp_pio::SFR_FSTAT_RX_EMPTY) & (self.sm_bitmask())) != 0

libs/xous-pio/src/pio_tests/mod.rs

@@ -5,19 +5,80 @@ pub mod adder;
 pub mod nec;
 
 #[cfg(not(any(target_os="xous", feature="rp2040")))]
-static mut REPORT_ADR: Option<*mut u32> = None;
+mod duart {
+    pub const UART_DOUT: utralib::Register = utralib::Register::new(0, 0xff);
+    pub const UART_DOUT_DOUT: utralib::Field = utralib::Field::new(8, 0, UART_DOUT);
+    pub const UART_CTL: utralib::Register = utralib::Register::new(1, 1);
+    pub const UART_CTL_EN: utralib::Field = utralib::Field::new(1, 0, UART_CTL);
+    pub const UART_BUSY: utralib::Register = utralib::Register::new(2, 1);
+    pub const UART_BUSY_BUSY: utralib::Field = utralib::Field::new(1, 0, UART_BUSY);
 
+    pub const HW_DUART_BASE: usize = 0x4004_2000;
+}
+
+#[cfg(not(any(target_os="xous", feature="rp2040")))]
+use utralib::CSR;
 #[cfg(not(any(target_os="xous", feature="rp2040")))]
-pub fn setup_reporting(rep_adr: *mut u32) {
-    unsafe {REPORT_ADR = Some(rep_adr);}
+pub struct Uart {
+}
+#[cfg(not(any(target_os="xous", feature="rp2040")))]
+impl Uart {
+    fn put_digit(&mut self, d: u8) {
+        let nyb = d & 0xF;
+        let c = if nyb < 10 {
+            nyb + 0x30
+        } else {
+            nyb + 0x61 - 10
+        };
+        assert!(c >= 0x30, "conversion failed!");
+        self.putc(c);
+    }
+    pub fn put_hex(&mut self, c: u8) {
+        self.put_digit(c >> 4);
+        self.put_digit(c & 0xF);
+    }
+    pub fn newline(&mut self) {
+        self.putc(0xd);
+    }
+    pub fn print_hex_word(&mut self, word: u32) {
+        for &byte in word.to_be_bytes().iter() {
+            self.put_hex(byte);
+        }
+    }
+    pub fn putc(&self, c: u8) {
+        let base = duart::HW_DUART_BASE as *mut u32;
+        let mut uart = CSR::new(base);
+
+        if uart.rf(duart::UART_CTL_EN) == 0 {
+            uart.wfo(duart::UART_CTL_EN, 1);
+        }
+        while uart.rf(duart::UART_BUSY_BUSY) != 0 {
+            // spin wait
+        }
+        uart.wfo(duart::UART_DOUT_DOUT, c as u32);
+
+        #[cfg(feature="arty")]
+        self.putc_litex(c);
+    }
+
+    pub fn tiny_write_str(&mut self, s: &str) {
+        for c in s.bytes() {
+            self.putc(c);
+        }
+    }
+
+}
+
+#[cfg(not(any(target_os="xous", feature="rp2040")))]
+pub fn setup_reporting(_rep_adr: *mut u32) {
 }
 
 pub fn report_api(d: u32) {
     #[cfg(not(any(target_os="xous", feature="rp2040")))]
-    unsafe {
-        if let Some(rep_adr) = REPORT_ADR {
-            rep_adr.write_volatile(d);
-        }
+    {
+        let mut uart = Uart {};
+        uart.print_hex_word(d);
+        uart.newline();
     }
     #[cfg(target_os="xous")]
     log::info!("report: 0x{:x}", d);