GitHub - azyzio/RiskCalculationFPGA: FPGA design for very fast Value at Risk calculation for Asian Options

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FPGA design for very fast Value at Risk calculation for Asian Options

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Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
_ngo		_ngo
_xmsgs		_xmsgs
ipcore_dir		ipcore_dir
iseconfig		iseconfig
memory_data		memory_data
xlnx_auto_0_xdb		xlnx_auto_0_xdb
.gitattributes		.gitattributes
.gitignore		.gitignore
CalculateExpMu.v		CalculateExpMu.v
CalculateExpSigma.v		CalculateExpSigma.v
MCCore.v		MCCore.v
Main.bld		Main.bld
Main.ngd		Main.ngd
Main.ngr		Main.ngr
Main.pad		Main.pad
Main.par		Main.par
Main.pcf		Main.pcf
Main.prj		Main.prj
Main.ptwx		Main.ptwx
Main.syr		Main.syr
Main.twr		Main.twr
Main.twx		Main.twx
Main.ucf		Main.ucf
Main.unroutes		Main.unroutes
Main.ut		Main.ut
Main.v		Main.v
Main.xdl		Main.xdl
Main.xpi		Main.xpi
Main.xst		Main.xst
Main_map.map		Main_map.map
Main_map.mrp		Main_map.mrp
Main_map.ngm		Main_map.ngm
Main_map.xrpt		Main_map.xrpt
Main_ngdbuild.xrpt		Main_ngdbuild.xrpt
Main_pad.csv		Main_pad.csv
Main_pad.txt		Main_pad.txt
Main_par.xrpt		Main_par.xrpt
Main_summary.html		Main_summary.html
Main_summary.xml		Main_summary.xml
Main_usage.xml		Main_usage.xml
Main_xst.xrpt		Main_xst.xrpt
RAM_X_18.v		RAM_X_18.v
ROM_3_13.v		ROM_3_13.v
ROM_path.v		ROM_path.v
RiskCalculationFPGA.gise		RiskCalculationFPGA.gise
RiskCalculationFPGA.xise		RiskCalculationFPGA.xise
SR_FF.v		SR_FF.v
flopoco.vhdl		flopoco.vhdl
main.bgn		main.bgn
main.bit		main.bit
main.drc		main.drc
main.ipf		main.ipf
main_bitgen.xwbt		main_bitgen.xwbt
pa.fromNcd.tcl		pa.fromNcd.tcl
planAhead_pid5512.debug		planAhead_pid5512.debug
test_CalculateExpSigma.v		test_CalculateExpSigma.v
test_ExpMu.v		test_ExpMu.v
test_Main.v		test_Main.v
wave_Main.wcfg		wave_Main.wcfg
wave_MuExp.wcfg		wave_MuExp.wcfg
wave_SigmaExp.wcfg		wave_SigmaExp.wcfg
webtalk_pn.xml		webtalk_pn.xml