Coding Style

All languages

(except where noted otherwise in the language's notes)

• One level of indentation = one \t character = four columns
• Maximum 120 characters per line
• BSD license header required at the top of each file (copy template from an existing file).
• Copyright date in headers should be changed to "2012-current year" when a file is modified (or created). Do not change copyright date on files at the start of a year "just because".
• Use CamelCase for multi-word identifier names
• Don't be afraid to use parentheses to clarify precedence even if not mandatory. Example: if( (foo == "bar") || (baz == 42) ). If an 8th grader can't tell the order of operations in your code, you're not using enough parentheses.
• Compiler warnings, or static analysis errors, are not tolerated. Fix your code or explicitly disable that warning for that line of code with a pragma or similar. In this case, you MUST comment to justify why the warning is a false positive.

C/C++

Generally use "ANSI" or "Visual Studio" style if in doubt.

• Use Doxygen-style comments on class and function declarations. Comment the class in the header and functions in the source file.
• Do not use a "C" prefix on class names.
• All global variables should have names prefixed with "g_"
• All member variables should have names prefixed with "m_"
• Curly braces go on their own line
• Macro names and enum values are all caps

Verilog

• Place "begin" declarations on the same line as the conditional.
• Indent multiple <= assignments, or signal declarations, in close proximity to the same level for readability.
• `default_nettype none and `timescale 1ns / 1ps must be the first two lines of every file.
• Do not use "=" assignments under any circumstances.
• Combinatorial "always" blocks must use "*" instead of an explicit sensitivity list.
• All parameters and ports must be named rather than specified by position.
• Use Verilog-2005 "one declaration" style for module ports when possible.
• Always specify default values for combinatorial blocks. Use of level-triggered latches for any reason is forbidden.
• Don't do any of the dumb things mentioned here https://github.com/azonenberg/openfpga/wiki/Linter-notes