GitHub - ashutosh321607/8-bit-RISC-processor-verilog: A 8 bit RISC Processor implemented in Verilog HDL and simulated in Vivado.

ashutosh321607 / 8-bit-RISC-processor-verilog Public

A 8 bit RISC Processor implemented in Verilog HDL and simulated in Vivado.

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
end_game		end_game
CONTRIBUTING.md		CONTRIBUTING.md
Music_Genre_Classification.ipynb		Music_Genre_Classification.ipynb
Music_genre_classification_NN.ipynb		Music_genre_classification_NN.ipynb