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Update Derecho Port (CICE-Consortium#974)
Update derecho port update inteloneapi, validate, use -O1, problems with -check all. update cray to ncarenv/23.09 and cce/16.0.1, answers change update intel to ncarenv/23.09 and intel/2023.2.1, answer bit-for-bit update nvhpc to ncarenv/23.09 and nvhpc/23.7, answers change update queue so smaller jobs go into develop (shared) instead of main Add ifndef __INTEL_LLVM_COMPILER (for intel oneapi) around an OMP loop that the compiler doesn't handle properly (reported to intel) in ice_history.F90. Update QC documentation in the user guide to clarify where/how to run the cice.t-test.py script.
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setenv ICE_MEMUSE 5 |
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