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1. AMBA_APB_Protocol AMBA_APB_Protocol Public

   Forked from yashgupta26/AMBA_APB_Protocol

   Verilog 2

2. APB-Master-Bridge APB-Master-Bridge Public

   Forked from YousefSherif/APB-Master-Bridge

   The master of APB bus is the bridge between the previous system bus and APB bus. This bridge is also a slave to the previous system bus. So, it has two interfaces, previous bus slave interface and …

   Verilog 1

3. Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB Public

   Forked from munim-sah75/Design-and-Simulation-of-a-32-bit-RISC-V-Core-and-APB

   A 32 Bit RISCV Core with APB protocol for data transfer written with SystemVerilog and verilog.

   SystemVerilog 1

4. MIPS32 MIPS32 Public

   Forked from skynatepro/MIPS32

   Design of 32-bit MIPS Processor

   Verilog 1

5. ASIC ASIC Public

   Forked from vlsi1217/ASIC

   EE 287 2012 Fall

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6. 100DaysofRTL 100DaysofRTL Public

   Forked from snbk001/100DaysofRTL

   100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priorit…

   SystemVerilog 1