This project is made using verilog on Xilinx. This will help in changing the pulse width of the output wave by using two signals that are increase duty cycle & decrease duty cycle.
Just unzip the PWMgenerator folder & open PWMgenerator.xise in xilinx software. Then run the test bench.
This project is taken from: https://www.fpga4student.com/2017/08/verilog-code-for-pwm-generator.html