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sigspec: decrease size with tagged union of bits and chunks #4490
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Original file line number | Diff line number | Diff line change |
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@@ -3791,6 +3791,8 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts) | |
width_ = 0; | ||
hash_ = 0; | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
log_assert(parts.size() > 0); | ||
auto ie = parts.begin(); | ||
auto it = ie + parts.size() - 1; | ||
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@@ -3802,6 +3804,8 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value) | |
{ | ||
cover("kernel.rtlil.sigspec.init.const"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (GetSize(value) != 0) { | ||
chunks_.emplace_back(value); | ||
width_ = chunks_.back().width; | ||
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@@ -3816,6 +3820,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value) | |
{ | ||
cover("kernel.rtlil.sigspec.init.const.move"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (GetSize(value) != 0) { | ||
chunks_.emplace_back(std::move(value)); | ||
width_ = chunks_.back().width; | ||
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@@ -3830,6 +3836,8 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk) | |
{ | ||
cover("kernel.rtlil.sigspec.init.chunk"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (chunk.width != 0) { | ||
chunks_.emplace_back(chunk); | ||
width_ = chunks_.back().width; | ||
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@@ -3844,6 +3852,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk) | |
{ | ||
cover("kernel.rtlil.sigspec.init.chunk.move"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (chunk.width != 0) { | ||
chunks_.emplace_back(std::move(chunk)); | ||
width_ = chunks_.back().width; | ||
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@@ -3858,6 +3868,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire) | |
{ | ||
cover("kernel.rtlil.sigspec.init.wire"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (wire->width != 0) { | ||
chunks_.emplace_back(wire); | ||
width_ = chunks_.back().width; | ||
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@@ -3872,6 +3884,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width) | |
{ | ||
cover("kernel.rtlil.sigspec.init.wire_part"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (width != 0) { | ||
chunks_.emplace_back(wire, offset, width); | ||
width_ = chunks_.back().width; | ||
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@@ -3886,6 +3900,8 @@ RTLIL::SigSpec::SigSpec(const std::string &str) | |
{ | ||
cover("kernel.rtlil.sigspec.init.str"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (str.size() != 0) { | ||
chunks_.emplace_back(str); | ||
width_ = chunks_.back().width; | ||
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@@ -3900,6 +3916,8 @@ RTLIL::SigSpec::SigSpec(int val, int width) | |
{ | ||
cover("kernel.rtlil.sigspec.init.int"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (width != 0) | ||
chunks_.emplace_back(val, width); | ||
width_ = width; | ||
|
@@ -3911,6 +3929,8 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width) | |
{ | ||
cover("kernel.rtlil.sigspec.init.state"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (width != 0) | ||
chunks_.emplace_back(bit, width); | ||
width_ = width; | ||
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@@ -3922,6 +3942,8 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width) | |
{ | ||
cover("kernel.rtlil.sigspec.init.bit"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
if (width != 0) { | ||
if (bit.wire == NULL) | ||
chunks_.emplace_back(bit.data, width); | ||
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@@ -3938,6 +3960,8 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks) | |
{ | ||
cover("kernel.rtlil.sigspec.init.stdvec_chunks"); | ||
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packed_ = true; | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
width_ = 0; | ||
hash_ = 0; | ||
for (const auto &c : chunks) | ||
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@@ -3949,6 +3973,8 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits) | |
{ | ||
cover("kernel.rtlil.sigspec.init.stdvec_bits"); | ||
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packed_ = false; | ||
(void)new (&this->bits_) std::vector<SigBit>(); | ||
width_ = 0; | ||
hash_ = 0; | ||
for (const auto &bit : bits) | ||
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@@ -3960,6 +3986,8 @@ RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits) | |
{ | ||
cover("kernel.rtlil.sigspec.init.pool_bits"); | ||
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packed_ = false; | ||
(void)new (&this->bits_) std::vector<SigBit>(); | ||
width_ = 0; | ||
hash_ = 0; | ||
for (const auto &bit : bits) | ||
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@@ -3971,6 +3999,8 @@ RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits) | |
{ | ||
cover("kernel.rtlil.sigspec.init.stdset_bits"); | ||
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packed_ = false; | ||
(void)new (&this->bits_) std::vector<SigBit>(); | ||
width_ = 0; | ||
hash_ = 0; | ||
for (const auto &bit : bits) | ||
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@@ -3982,6 +4012,8 @@ RTLIL::SigSpec::SigSpec(bool bit) | |
{ | ||
cover("kernel.rtlil.sigspec.init.bool"); | ||
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packed_ = false; | ||
(void)new (&this->bits_) std::vector<SigBit>(); | ||
width_ = 0; | ||
hash_ = 0; | ||
append(SigBit(bit)); | ||
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@@ -3992,13 +4024,13 @@ void RTLIL::SigSpec::pack() const | |
{ | ||
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; | ||
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if (that->bits_.empty()) | ||
if (packed_ || that->bits_.empty()) | ||
return; | ||
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cover("kernel.rtlil.sigspec.convert.pack"); | ||
log_assert(that->chunks_.empty()); | ||
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std::vector<RTLIL::SigBit> old_bits; | ||
std::vector<RTLIL::SigChunk> new_chunks; | ||
old_bits.swap(that->bits_); | ||
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RTLIL::SigChunk *last = NULL; | ||
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@@ -4016,31 +4048,37 @@ void RTLIL::SigSpec::pack() const | |
continue; | ||
} | ||
} | ||
that->chunks_.push_back(bit); | ||
last = &that->chunks_.back(); | ||
new_chunks.push_back(bit); | ||
last = &new_chunks.back(); | ||
last_end_offset = bit.offset + 1; | ||
} | ||
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that->bits_.~vector(); | ||
that->packed_ = true; | ||
(void)new (&that->chunks_) std::vector<SigChunk>(std::move(new_chunks)); | ||
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check(); | ||
} | ||
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void RTLIL::SigSpec::unpack() const | ||
{ | ||
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this; | ||
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if (that->chunks_.empty()) | ||
if (!packed_ || that->chunks_.empty()) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Analogously here |
||
return; | ||
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cover("kernel.rtlil.sigspec.convert.unpack"); | ||
log_assert(that->bits_.empty()); | ||
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that->bits_.reserve(that->width_); | ||
std::vector<RTLIL::SigBit> new_bits; | ||
new_bits.reserve(that->width_); | ||
for (auto &c : that->chunks_) | ||
for (int i = 0; i < c.width; i++) | ||
that->bits_.emplace_back(c, i); | ||
new_bits.emplace_back(c, i); | ||
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that->chunks_.clear(); | ||
that->hash_ = 0; | ||
that->chunks_.~vector(); | ||
that->packed_ = false; | ||
(void)new (&that->bits_) std::vector<SigBit>(std::move(new_bits)); | ||
} | ||
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void RTLIL::SigSpec::updhash() const | ||
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@@ -4620,7 +4658,6 @@ void RTLIL::SigSpec::check(Module *mod) const | |
w += chunk.width; | ||
} | ||
log_assert(w == width_); | ||
log_assert(bits_.empty()); | ||
} | ||
else | ||
{ | ||
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@@ -4631,9 +4668,7 @@ void RTLIL::SigSpec::check(Module *mod) const | |
if (bits_[i].wire != nullptr) | ||
log_assert(bits_[i].wire->module == mod); | ||
} | ||
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log_assert(width_ == GetSize(bits_)); | ||
log_assert(chunks_.empty()); | ||
} | ||
} | ||
#endif | ||
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Original file line number | Diff line number | Diff line change |
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@@ -838,24 +838,27 @@ struct RTLIL::SigSpecConstIterator | |
inline void operator++() { index++; } | ||
}; | ||
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struct RTLIL::SigSpec | ||
struct alignas(64) RTLIL::SigSpec | ||
{ | ||
private: | ||
int width_; | ||
bool packed_; | ||
unsigned long hash_; | ||
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0 | ||
std::vector<RTLIL::SigBit> bits_; // LSB at index 0 | ||
union { | ||
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0 | ||
std::vector<RTLIL::SigBit> bits_; // LSB at index 0 | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Could we do this with There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Good idea, this is a good small but hot case to try it on |
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}; | ||
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void pack() const; | ||
void unpack() const; | ||
void updhash() const; | ||
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inline bool packed() const { | ||
return bits_.empty(); | ||
return packed_; | ||
} | ||
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inline void inline_unpack() const { | ||
if (!chunks_.empty()) | ||
if (packed_ && !chunks_.empty()) | ||
unpack(); | ||
} | ||
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@@ -864,8 +867,47 @@ struct RTLIL::SigSpec | |
friend struct RTLIL::Module; | ||
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public: | ||
SigSpec() : width_(0), hash_(0) {} | ||
SigSpec() : width_(0), packed_(true), hash_(0), chunks_() {} | ||
~SigSpec() { if (packed_) chunks_.~vector(); else bits_.~vector(); } | ||
SigSpec(std::initializer_list<RTLIL::SigSpec> parts); | ||
SigSpec(const Yosys::RTLIL::SigSpec &other) | ||
{ | ||
packed_ = other.packed_; | ||
width_ = other.width_; | ||
hash_ = other.hash_; | ||
if (packed_) { | ||
(void)new (&this->chunks_) std::vector<SigChunk>(); | ||
chunks_ = other.chunks_; | ||
} else { | ||
(void)new (&this->bits_) std::vector<SigBit>(); | ||
bits_ = other.bits_; | ||
} | ||
check(); | ||
} | ||
SigSpec& operator=(const Yosys::RTLIL::SigSpec & other) | ||
{ | ||
if (packed_ != other.packed_) { | ||
if (packed_) { | ||
chunks_.~vector(); | ||
packed_ = false; | ||
(void)new (&bits_) std::vector<SigBit>(other.bits_); | ||
} else { | ||
bits_.~vector(); | ||
packed_ = true; | ||
(void)new (&chunks_) std::vector<SigChunk>(other.chunks_); | ||
} | ||
} else { | ||
if (packed_) | ||
chunks_ = other.chunks_; | ||
else | ||
bits_ = other.bits_; | ||
} | ||
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width_ = other.width_; | ||
hash_ = other.hash_; | ||
check(); | ||
return *this; | ||
} | ||
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SigSpec(const RTLIL::Const &value); | ||
SigSpec(RTLIL::Const &&value); | ||
|
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Shouldn't we be removing the
bits_.empty()
check? We need to guarantee accesses tochunks_
are valid oncepack()
returns, so we need to do the switch in full no matter ifbits_
are empty.