Skip to content

Commit

Permalink
[vivado] fix removing required newline in TCL scripts
Browse files Browse the repository at this point in the history 
fix vivado_postsynth_sim write_netlist
  • Loading branch information
@kammoh
kammoh committed Feb 21, 2024
1 parent 256049c commit f0cf42a
Show file tree
Hide file tree
Showing 4 changed files with 31 additions and 31 deletions.
38 changes: 19 additions & 19 deletions src/xeda/flows/vivado/templates/vivado_alt_synth.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ if {[lsearch -exact $parts $fpga_part] < 0} {
puts "Targeting device: $fpga_part"

{% for src in design.rtl.sources %}
{%- if src.type.name == "Verilog" %}
{% if src.type.name == "Verilog" %}
puts "Reading Verilog file {{src.file}}"
if { [catch {eval read_verilog {{src.file}} } myError]} {
errorExit $myError
Expand All @@ -53,7 +53,7 @@ if { [catch {eval read_verilog -sv {{src.file}} } myError]} {
}
{%- elif src.type.name == "Vhdl" %}
puts "Reading VHDL file {{src.file}}"
if { [catch {eval read_vhdl {%- if design.language.vhdl.standard == "08" %} -vhdl2008 {%- endif %} {{src.file}} } myError]} {
if { [catch {eval read_vhdl {% if design.language.vhdl.standard == "08" %} -vhdl2008 {%- endif %} {{src.file}} } myError]} {
errorExit $myError
}
{%- endif %}
Expand All @@ -69,19 +69,19 @@ read_xdc {{xdc_file}}
puts "\n===========================( RTL Synthesize and Map )==========================="
eval synth_design -part $fpga_part -top {{design.rtl.top}} {{settings.synth.steps.synth|flatten_options}} {{design.rtl.generics|vivado_generics}}

{%- if settings.synth.strategy == "Debug" %}
{% if settings.synth.strategy == "Debug" %}
set_property KEEP_HIERARCHY true [get_cells -hier * ]
set_property DONT_TOUCH true [get_cells -hier * ]
{%- endif %}
showWarningsAndErrors


{%- if settings.synth.steps.opt is not none %}
{% if settings.synth.steps.opt is not none %}
puts "\n==============================( Optimize Design )================================"
eval opt_design {{settings.synth.steps.opt|flatten_options}}
{%- endif %}

{%- if settings.write_checkpoint %}
{% if settings.write_checkpoint %}
write_checkpoint -force ${checkpoints_dir}/post_synth
{%- endif %}
report_timing_summary -file ${reports_dir}/post_synth/timing_summary.rpt
Expand All @@ -91,7 +91,7 @@ report_utilization -hierarchical -force -file ${reports_dir}/post_synth/hierarch

{# post-synth and post-place power optimization steps are mutually exclusive! #}
{# TODO: check this is still the case with the most recent versions of Vivado #}
{%- if settings.synth.steps.power_opt and not settings.impl.steps.power_opt %}
{% if settings.synth.steps.power_opt and not settings.impl.steps.power_opt %}
puts "\n===============================( Post-synth Power Optimization )================================"
# this is more effective than Post-placement Power Optimization but can hurt timing
eval power_opt_design
Expand All @@ -104,37 +104,37 @@ eval place_design {{settings.impl.steps.place|flatten_options}}
showWarningsAndErrors


{%- if settings.impl.steps.power_opt %}
{% if settings.impl.steps.power_opt %}
puts "\n===============================( Post-placement Power Optimization )================================"
eval power_opt_design
report_power_opt -file ${reports_dir}/post_place/post_place_power_optimization.rpt
showWarningsAndErrors
{%- endif %}

{%- if settings.impl.steps.place_opt is not none %}
{% if settings.impl.steps.place_opt is not none %}

puts "\n==============================( Post-place optimization )================================"
eval opt_design {{settings.impl.steps.place_opt|flatten_options}}

{%- if settings.impl.steps.place_opt2 is not none %}
{% if settings.impl.steps.place_opt2 is not none %}
puts "\n==============================( Post-place optimization 2)================================"
eval opt_design {{settings.impl.steps.place_opt2|flatten_options}}
{%- endif %}

{%- endif %}


{%- if settings.impl.steps.phys_opt is not none %}
{% if settings.impl.steps.phys_opt is not none %}
puts "\n========================( Post-place Physical Optimization )=========================="
eval phys_opt_design {{settings.impl.steps.phys_opt|flatten_options}}

{%- if settings.impl.steps.phys_opt is not none %}
{% if settings.impl.steps.phys_opt is not none %}
puts "\n========================( Post-place Physical Optimization 2 )=========================="
eval phys_opt_design {{settings.impl.steps.phys_opt|flatten_options}}
{%- endif %}
{%- endif %}

{%- if settings.write_checkpoint %}
{% if settings.write_checkpoint %}
write_checkpoint -force ${checkpoints_dir}/post_place
report_timing_summary -file ${reports_dir}/post_place/timing_summary.rpt
report_utilization -hierarchical -force -file ${reports_dir}/post_place/hierarchical_utilization.rpt
Expand All @@ -144,13 +144,13 @@ puts "\n================================( Route Design )========================
eval route_design {{settings.impl.steps.route|flatten_options}}
showWarningsAndErrors

{%- if settings.impl.steps.post_route_phys_opt is not none %}
{% if settings.impl.steps.post_route_phys_opt is not none %}
puts "\n=========================( Post-Route Physical Optimization )=========================="
phys_opt_design {{settings.impl.steps.post_route_phys_opt|flatten_options}}
showWarningsAndErrors
{%- endif %}

{%- if settings.write_checkpoint %}
{% if settings.write_checkpoint %}
puts "\n=============================( Writing Checkpoint )=============================="
write_checkpoint -force ${checkpoints_dir}/post_route
{%- endif %}
Expand All @@ -167,14 +167,14 @@ report_utilization -file [file join ${rep_dir} utilization.rpt]
report_utilization -file [file join ${rep_dir} utilization.xml] -format xml
report_utilization -hierarchical -file [file join ${rep_dir} hierarchical_utilization.xml] -format xml

{%- if settings.extra_reports %}
{% if settings.extra_reports -%}
report_clock_utilization -file [file join ${rep_dir} clock_utilization.rpt]
report_power -file [file join ${rep_dir} power.rpt]
report_drc -file [file join ${rep_dir} drc.rpt]
report_methodology -file [file join ${rep_dir} methodology.rpt]
{%- endif %}

{%- if settings.qor_suggestions %}
{% if settings.qor_suggestions -%}
report_qor_suggestions -file [file join ${rep_dir} qor_suggestions.rpt]
{%- endif %}

Expand All @@ -185,13 +185,13 @@ if {[string is double -strict $timing_slack]} {

if {[string is double -strict $timing_slack] && ($timing_slack < 0)} {
puts "ERROR: Failed to meet timing by $timing_slack, see ${timing_summary_file} for details"
{%- if settings.fail_timing %}
{% if settings.fail_timing %}
exit 1
{%- endif %}
}
}

{%- if settings.write_netlist %}
{% if settings.write_netlist -%}
puts "\n==========================( Writing Netlist and SDF )============================="
write_verilog -mode funcsim -force ${settings.outputs_dir}/impl_funcsim.v
write_sdf -mode timesim -process_corner slow -force -file ${settings.outputs_dir}/impl_timesim.sdf
Expand All @@ -201,7 +201,7 @@ write_verilog -mode timesim -sdf_anno false -force -file ${settings.outputs_dir}
write_xdc -no_fixed_only -force ${settings.outputs_dir}/impl.xdc
{%- endif %}

{%- if settings.write_bitstream %}
{% if settings.write_bitstream -%}
puts "\n==============================( Writing Bitstream )==============================="
write_bitstream -force ${settings.outputs_dir}/bitstream.bit
{%- endif %}
Expand Down
8 changes: 4 additions & 4 deletions src/xeda/flows/vivado/templates/vivado_report_helper.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ if {$ACTIVE_STEP == "route_design"} {
set timing_slack [get_property SLACK [get_timing_paths]]
puts "Final timing slack: $timing_slack ns"

{%- if settings.qor_suggestions %}
{% if settings.qor_suggestions %}
report_qor_suggestions -quiet -max_strategies 5 -file [file join ${reports_dir} qor_suggestions.rpt]
write_qor_suggestions -quiet -strategy_dir ./strategy_suggestions -force ./qor_suggestions.rqs
{%- endif %}
Expand All @@ -27,12 +27,12 @@ if {$ACTIVE_STEP == "route_design"} {
puts "ERROR: Failed to meet timing by $timing_slack, see [file join ${reports_dir} post_route timing_summary.rpt] for details"
puts "\n===========================( *DISABLE ECHO* )==========================="

{%- if settings.fail_timing %}
{% if settings.fail_timing %}
exit 1
{%- endif %}
}

{%- if settings.write_netlist -%}
{% if settings.write_netlist -%}
puts "\n==========================( Writing netlists and SDF )=========================="
write_verilog -mode timesim -sdf_anno false -force -file ${outputs_dir}/timesim.v
write_sdf -mode timesim -process_corner slow -force -file ${outputs_dir}/timesim.min.sdf
Expand All @@ -41,7 +41,7 @@ if {$ACTIVE_STEP == "route_design"} {
write_xdc -no_fixed_only -force ${outputs_dir}/impl.xdc
{%- endif %}

{%- if settings.write_bitstream %}
{% if settings.write_bitstream %}
puts "\n===========================( Writing bitstream )================================="
write_bitstream -force {{design.rtl.top}}.bit
{%- endif %}
Expand Down
14 changes: 7 additions & 7 deletions src/xeda/flows/vivado/templates/vivado_synth.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ set_msg_config -id "\[{{msg}}\]" -suppress

puts "\n=====================( Read Design Files and Constraints )====================="
{%- for src in design.rtl.sources %}
{%- if src.type.name == "Verilog" %}
{% if src.type.name == "Verilog" %}
puts "Reading Verilog file {{src.file}}"
if { [catch {eval read_verilog {{src.file}} } myError]} {
errorExit $myError
Expand Down Expand Up @@ -52,20 +52,20 @@ set_property strategy {{settings.synth.strategy}} [get_runs synth_1]
set avail_impl_strategies [join [list_property_value strategy [get_runs impl_1] ] " "]
puts "\n Available implementation strategies:\n $avail_impl_strategies\n"

{%- if settings.impl.strategy %}
{% if settings.impl.strategy %}
puts "Using {{settings.impl.strategy}} strategy for implementation."
set_property strategy {{settings.impl.strategy}} [get_runs impl_1]
{%- endif %}

{%- if generics %}
{% if generics %}
set_property generic {% raw -%} { {%- endraw -%} {{generics}} {%- raw -%} } {%- endraw %} [current_fileset]
{%- endif %}

#{# see https://www.xilinx.com/support/documentation/sw_manuals/xilinx2022_1/ug912-vivado-properties.pdf #}
#{# and https://www.xilinx.com/support/documentation/sw_manuals/xilinx2022_1/ug835-vivado-tcl-commands.pdf #}
{%- for step,options in settings.synth.steps.items() %}
{%- for name,value in options.items() %}
{%- if value is mapping %}
{% if value is mapping %}
{%- for k,v in value.items() %}
set_property STEPS.{{step}}.{{name}}.{{k}} {{v}} [get_runs synth_1]
{%- endfor %}
Expand All @@ -77,7 +77,7 @@ set_property STEPS.{{step}}.{{name}} {{value}} [get_runs synth_1]

{%- for step,options in settings.impl.steps.items() %}
{%- for name,value in options.items() %}
{%- if value is mapping %}
{% if value is mapping %}
{%- for k,v in value.items() %}
set_property STEPS.{{step}}.{{name}}.{{k}} {{v}} [get_runs impl_1]
{%- endfor %}
Expand All @@ -96,12 +96,12 @@ set_property STEPS.ROUTE_DESIGN.TCL.POST [pwd]/{{reports_tcl}} [get_runs impl_1]
# create_report_config -report_type report_utilization -report_name post_route_hier_report -steps route_design -runs [get_runs impl_1] -options {-hierarchical -format xml}

puts "\n=============================( Running Synthesis )============================="
launch_runs synth_1 {%- if settings.nthreads %} -jobs {{settings.nthreads}} {%- endif %}
launch_runs synth_1 {% if settings.nthreads %} -jobs {{settings.nthreads}} {%- endif %}
wait_on_run synth_1
# renamed to wait_on_runs in Vivado 2021.2

puts "\n===========================( Running Implementation )=========================="
launch_runs impl_1 {%-if settings.nthreads %} -jobs {{settings.nthreads}} {%- endif %} {%- if not settings.write_bitstream %} -to_step route_design {%- endif %}
launch_runs impl_1 {%-if settings.nthreads %} -jobs {{settings.nthreads}} {%- endif %} {% if not settings.write_bitstream %} -to_step route_design {%- endif %}
wait_on_run impl_1

puts "\n====================================( DONE )==================================="
2 changes: 1 addition & 1 deletion src/xeda/flows/vivado/vivado_postsynthsim.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ def init(self) -> None:
ss.synth.input_delay = input_delay
if ss.synth.output_delay is None:
ss.synth.output_delay = 0.0
ss.synth.write_netlist = True
ss.synth.write_netlist = True
self.add_dependency(VivadoSynth, ss.synth)

def run(self) -> None:
Expand Down

0 comments on commit f0cf42a

Please sign in to comment.