improve yosys settings and parsing

src/xeda/flow_runner/remote.py

@@ -104,7 +104,7 @@ def remote_runner(channel, remote_path, zip_file, flow, design_file, flow_settin
     launcher = DefaultRunner(
         xeda_run_dir,
         cached_dependencies=True,
-        backups=True,
+        backups=False,
         cleanup_before_run=True,
         incremental=False,
         post_cleanup=False,
@@ -149,6 +149,7 @@ def cb(self, data):
 class RemoteRunner(FlowLauncher):
     class Settings(FlowLauncher.Settings):
         clean: bool = True
+        backups: bool = False
 
     def run_remote(
         self,

src/xeda/flows/yosys/templates/read_files.tcl

@@ -11,17 +11,17 @@ yosys plugin -i systemverilog
 
 {%- for src in design.rtl.sources %}
 {%- if src.type.name == "Verilog" or (not uhdm_plugin and src.type.name == "SystemVerilog") %}
-yosys log -stdout "Reading {{src}}"
+yosys log -stdout "** Reading {{src}} **"
 yosys read_verilog -defer {{settings.read_verilog_flags|join(" ")}} {{defines|join(" ")}} {{src}}
 {%- elif src.type.name == "SystemVerilog" %}
-yosys log -stdout "Reading {{src}}"
+yosys log -stdout "** Reading {{src}} **"
 yosys read_systemverilog -defer {{settings.read_systemverilog_flags|join(" ")}} {{src}}
 {%- endif %}
 {%- endfor %}
 
 {% set vhdl_files = design.sources_of_type("Vhdl", rtl=true, tb=false) %}
 {%- if vhdl_files %}
-yosys log -stdout "Elaborating VHDL files"
+yosys log -stdout "** Elaborating VHDL files **"
 yosys plugin -i ghdl
 yosys ghdl {{ghdl_args|join(" ")}}
 {% endif %}

src/xeda/flows/yosys/templates/yosys.ys

@@ -1,3 +1,5 @@
+yosys logger -notime -stderr
+
 {% for src in design.rtl.sources %}
 {%- if src.type == 'verilog' %}
 log -stdout yosys> Reading {{src}}

src/xeda/flows/yosys/templates/yosys_fpga_synth.tcl

@@ -1,4 +1,5 @@
 
+yosys logger -notime -stderr
 {% include 'read_files.tcl' %}
 
 {% if settings.prep is not none %}
@@ -12,20 +13,31 @@ yosys flatten
 
 {% include "post_rtl.tcl" %}
 
-yosys log -stdout "Running FPGA synthesis for device {{settings.fpga}}"
+{% if settings.pre_synth_opt %}
+yosys log -stdout "** Pre-synthesis optimization **"
+yosys opt -full -purge -sat
+{% endif %}
+
+{% if settings.abc9 -%}
+{% if settings.flow3 %} yosys scratchpad -copy abc9.script.flow3 abc9.script {% endif %}
+{# decrease the target delay to account for interconnect delay #}
+{% if settings.main_clock and settings.main_clock.period_ps %} yosys scratchpad -set abc9.D {{settings.main_clock.period_ps / 1.5}} {% endif %}
+{%- endif %}
+
+yosys log -stdout "** FPGA synthesis for device {{settings.fpga}} **"
 {% if settings.fpga.vendor == "xilinx" %}
-yosys log -stdout "Target: Xilinx {%if settings.fpga.part%} {{settings.fpga.part}} {%else%} {{settings.fpga.device}} {%endif%}"
+yosys log -stdout "*** Target: Xilinx {%if settings.fpga.part%} {{settings.fpga.part}} {%else%} {{settings.fpga.device}} {%endif%} ***"
 yosys synth_xilinx {% if settings.fpga.family %} -family {{settings.fpga.family}} {% endif %} {{settings.synth_flags|join(" ")}}
 {% elif settings.fpga.family %}
-yosys log -stdout " Target: {{settings.fpga.family}}"
+yosys log -stdout "*** Target: {{settings.fpga.family}} ***"
 yosys synth_{{settings.fpga.family}} {{settings.synth_flags|join(" ")}} {% if design.rtl.top %} -top {{design.rtl.top}}{% endif %}
 {% else %}
-yosys log -stdout "Unknown FPGA vendor, family, or device"
+yosys log -stdout "[ERROR] Unknown FPGA vendor, family, or device"
 {% endif %}
 
 
 {% if settings.post_synth_opt %}
-yosys log -stdout "Post-synth optimization"
+yosys log -stdout "** Post-synthesis optimization **"
 yosys opt -full -purge -sat
 {% endif %}
 

src/xeda/flows/yosys/templates/yosys_synth.tcl

@@ -1,3 +1,4 @@
+yosys logger -notime -stderr
 {% include 'read_files.tcl' %}
 
 {% if settings.prep is not none %}

src/xeda/flows/yosys/yosys_fpga.py

@@ -17,6 +17,9 @@ class YosysFpga(YosysBase, FpgaSynthFlow):
 
     class Settings(YosysBase.Settings, FpgaSynthFlow.Settings):
         abc9: bool = Field(True, description="Use abc9")
+        flow3: bool = Field(
+            True, description="Use flow3, which runs the mapping several times, if abc9 is set"
+        )
         retime: bool = Field(False, description="Enable flip-flop retiming")
         nobram: bool = Field(False, description="Do not map to block RAM cells")
         nodsp: bool = Field(False, description="Do not use DSP resources")
@@ -26,19 +29,22 @@ class Settings(YosysBase.Settings, FpgaSynthFlow.Settings):
             description="Run a simple static timing analysis (requires `flatten`)",
         )
         nowidelut: bool = Field(
-            False,
+            True,
             description="Do not use MUX resources to implement LUTs larger than native for the target",
         )
-        abc_dff: bool = Field(True, description="Run abc/abc9 with -dff option")
+        abc_dff: bool = Field(False, description="Run abc/abc9 with -dff option")
         widemux: int = Field(
             0,
             description="enable inference of hard multiplexer resources for muxes at or above this number of inputs"
             " (minimum value 2, recommended value >= 5 or disabled = 0)",
         )
         synth_flags: List[str] = []
-        abc_flags: List[str] = []
+        pre_synth_opt: bool = Field(
+            False,
+            description="run additional optimization steps before synthesis",
+        )
         post_synth_opt: bool = Field(
-            True,
+            False,
             description="run additional optimization steps after synthesis if complete",
         )
         optimize: Optional[Literal["speed", "area"]] = Field(
@@ -146,18 +152,20 @@ def parse_reports(self) -> bool:
                     if ram32m:
                         self.results["LUT"] += ram32m
                         self.results["LUT:RAM"] = ram32m
-                    self.results["FF"] = sum_all_resources(design_util, ["FDRE", "FDSE"])
-                    carry4 = sum_all_resources(design_util, ["CARRY4"])
-                    if carry4:
-                        self.results["CARRY"] = carry4
+                    self.results["FF"] = sum_all_resources(
+                        design_util, ["FDCE", "FDPE", "FDRE", "FDSE"]
+                    )
                     brams = sum_all_resources(design_util, ["RAMB36"])
                     brams_half = sum_all_resources(design_util, ["RAMB18"])
                     brams += brams_half / 2
                     if brams:
                         self.results["BRAM"] = brams
-                    dsps = sum_all_resources(design_util, ["DSP48E"])
+                    dsps = sum_all_resources(design_util, ["DSP48E1", "DSP48E2", "DSP48E"])
                     if dsps:
                         self.results["DSP"] = dsps
+                    carry_chains = sum_all_resources(design_util, ["CARRY4", "CARRY2"])
+                    if carry_chains:
+                        self.results["CARRY"] = carry_chains
 
         # if self.settings.fpga:
         return True