RiscV_verilog is a student project created o teste the RiscV ISA, here i have implemetended a very simple hert RiscV
To teste and possible deploy on FPGA you will need the Quartus Primer and ModelSim Lite version will work fine. After that just clone the repository and import the *.v files in one Verilog project.
Some times the ram module (Intel IP RAM) have some problems to import in the project so maybe you will have to to create your own is very simple, just rementer to set the follow options.
- Do not register the output Q
- Set riscV_victor.hex as memory initiation file
- The output must be 8 bits
- Has at least 16k of memory
Install Quatus Primer Lite and ModelSim from Intel Site
Is import have the RiscV Toolchain from , when building the toolchain remember to run the build script build-rv32ima.sh
Explain how to run the automated tests for this system
Explain what these tests test and why
Give an example
Explain what these tests test and why
Give an example
Add additional notes about how to deploy this on a live system
- RiscV - The ISA used
- Victor Lacerda - Initial work - VictorGerin
This project is licensed under the GNU License - see the LICENSE.md file for details
- All members of RiscV project and there awesome manual