v1.1.2 for Vivado

PoC v1.1.2 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).

v1.1.2

This minor update adds constraint files for the Xilinx Artix-7 FPGA AC701 Evaluation Kit.

v1.1.1 for Vivado

PoC v1.1.1 with workarounds required for Xilinx Vivado (at least up to Vivado 2016.2).

v1.1.1

This release contains:

• A bigger and improved documentation including command line tools and the Python infrastructure
• ModelSim support
• UVVM integration
• Continuous Integration on AppVeyor
• Improved cache IP cores and better ocram simulation models
• Improved testbenches: e.g. sorting networks tested with OSVVMs scoreboard.

v1.1.0

Finalized milestone 1.1.

v1.0.1

Minor fixes for the first major release including the new Python infrastructure.

First PoC release

First major release of PoC including the new Python infrastructure.