feat: adapt for wokwi projects

.github/workflows/gds.yaml

@@ -25,18 +25,6 @@ jobs:
       - name: Run Tiny Tapeout Precheck
         uses: TinyTapeout/tt-gds-action/precheck@tt09
 
-  gl_test:
-    needs: gds
-    runs-on: ubuntu-latest
-    steps:
-      - name: checkout repo
-        uses: actions/checkout@v4
-        with:
-          submodules: recursive
-
-      - name: GL test
-        uses: TinyTapeout/tt-gds-action/gl_test@tt09
-
   viewer:
     needs: gds
     runs-on: ubuntu-latest

.github/workflows/test.yaml → .github/workflows/wokwi_test.yaml

@@ -1,14 +1,21 @@
-name: test
+name: wokwi_test
 on: [push, workflow_dispatch]
 jobs:
-  test:
+  wokwi_test:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout repo
         uses: actions/checkout@v4
         with:
           submodules: recursive
 
+      - name: Checkout tt-support-tools repo
+        uses: actions/checkout@v4
+        with:
+          repository: TinyTapeout/tt-support-tools
+          path: tt
+          ref: tt09
+
       - name: Install iverilog
         shell: bash
         run: sudo apt-get update && sudo apt-get install -y iverilog
@@ -21,9 +28,21 @@ jobs:
 
       - name: Install Python packages
         shell: bash
-        run: pip install -r test/requirements.txt
+        run: |
+          pip install -r test/requirements.txt
+          pip install -r tt/requirements.txt
+
+      - name: Fetch the truth table
+        run: ./tt/tt_tool.py --create-user-config
+
+      - name: Check for truth table existence
+        id: check_files
+        uses: andstor/file-existence-action@v3
+        with:
+          files: "test/truthtable.md"
 
       - name: Run tests
+        if: steps.check_files.outputs.files_exists == 'true'
         run: |
           cd test
           make clean
@@ -43,5 +62,5 @@ jobs:
         with:
           name: test-vcd
           path: |
-            test/tb.vcd
+            test/*.vcd
             test/results.xml

README.md

@@ -1,6 +1,6 @@
-![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
+![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/wokwi_test/badge.svg) ![](../../workflows/fpga/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+# Tiny Tapeout Wokwi Project Template
 
 - [Read the documentation for project](docs/info.md)
 
@@ -10,14 +10,11 @@ Tiny Tapeout is an educational project that aims to make it easier and cheaper t
 
 To learn more and get started, visit https://tinytapeout.com.
 
-## Set up your Verilog project
+## Wokwi Projects
 
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
-3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.
+Edit the [info.yaml](info.yaml) and change the `wokwi_id` to the ID of your Wokwi project. You can find the ID in the URL of your project, it's the big number after `wokwi.com/projects/`.
 
-The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
+The GitHub action will automatically fetch the digital netlist from Wokwi and build the ASIC files.
 
 ## Enable GitHub actions to build the results page
 

info.yaml

@@ -1,23 +1,16 @@
-# Tiny Tapeout project information
+# Tiny Tapeout project information (Wokwi project)
 project:
+  wokwi_id:     0       # Set this to the ID of your Wokwi project (the number from the project's URL)
   title:        ""      # Project title
   author:       ""      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
-  # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
-
-  # List your project's source files here.
-  # Source files must be in ./src and you must list each source file separately, one per line.
-  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
-  source_files:
-    - "project.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

src/cells.v

@@ -0,0 +1,102 @@
+/*
+This file provides the mapping from the Wokwi modules to Verilog HDL.
+
+It's only needed for Wokwi designs.
+*/
+
+`define default_netname none
+
+module buffer_cell (
+    input wire in,
+    output wire out
+    );
+    assign out = in;
+endmodule
+
+module and_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a & b;
+endmodule
+
+module or_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a | b;
+endmodule
+
+module xor_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a ^ b;
+endmodule
+
+module nand_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = !(a&b);
+endmodule
+
+module not_cell (
+    input wire in,
+    output wire out
+    );
+
+    assign out = !in;
+endmodule
+
+module mux_cell (
+    input wire a,
+    input wire b,
+    input wire sel,
+    output wire out
+    );
+
+    assign out = sel ? b : a;
+endmodule
+
+module dff_cell (
+    input wire clk,
+    input wire d,
+    output reg q,
+    output wire notq
+    );
+
+    assign notq = !q;
+    always @(posedge clk)
+        q <= d;
+
+endmodule
+
+module dffsr_cell (
+    input wire clk,
+    input wire d,
+    input wire s,
+    input wire r,
+    output reg q,
+    output wire notq
+    );
+
+    assign notq = !q;
+
+    always @(posedge clk or posedge s or posedge r) begin
+        if (r)
+            q <= 0;
+        else if (s)
+            q <= 1;
+        else
+            q <= d;
+    end
+endmodule