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feat: update project tt_um_phansel_laplace_lut from phansel/ttihp-ens2
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Commit: dfa58d4be9ed83e8eb66d2b9d2715cb323bd295a
Workflow: https://github.com/phansel/ttihp-ens2/actions/runs/11645644338
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TinyTapeoutBot authored and urish committed Nov 3, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_phansel_laplace_lut/commit_id.json
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{
"app": "Tiny Tapeout tt09 b176ed7c",
"repo": "https://github.com/phansel/ttihp-ens2",
"commit": "b40eb0485a1097dda7c0744f8dfe94170142f052",
"workflow_url": "https://github.com/phansel/ttihp-ens2/actions/runs/11624660587",
"commit": "dfa58d4be9ed83e8eb66d2b9d2715cb323bd295a",
"workflow_url": "https://github.com/phansel/ttihp-ens2/actions/runs/11645644338",
"sort_id": 1730216535727
}
4 changes: 2 additions & 2 deletions projects/tt_um_phansel_laplace_lut/docs/info.md
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Expand Up @@ -10,9 +10,9 @@ The read-only Verilog containing the actual ASCII data is generated by a python

## How to test

Program a number onto ui_in[5:0] between 0 and 43. Toggle reset_n (high/low/high), then toggle ui_in[6] high to start printing. Watch uo_out and uio_out for the resulting ASCII characters.
Program a number onto ui_in[5:0] between 0 and 46. Toggle reset_n (high/low/high), then toggle ui_in[6] high to start printing. Watch uo_out and uio_out for the resulting ASCII characters.

The input address bus accepts a number (0-45) corresponding to an arbitrary Laplace tranform encoding; it must be set before asserting start. The active-high character output enable signal must be high to start or continue character output. The clock divider disable input must be high to run at full speed or low to run at 1 character per 5x10^7 clocks.
The input address bus accepts a number (0-46) corresponding to an arbitrary Laplace tranform encoding; it must be set before asserting start. The active-high character output enable signal must be high to start or continue character output. The clock divider disable input must be high to run at full speed or low to run at 1 character per 5x10^7 clocks.

## External hardware

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286 changes: 148 additions & 138 deletions projects/tt_um_phansel_laplace_lut/stats/metrics.csv

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72 changes: 34 additions & 38 deletions projects/tt_um_phansel_laplace_lut/stats/synthesis-stats.txt
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=== tt_um_phansel_laplace_lut ===

Number of wires: 3193
Number of wire bits: 3228
Number of wires: 3199
Number of wire bits: 3234
Number of public wires: 73
Number of public wire bits: 108
Number of ports: 8
Number of port bits: 43
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 3131
sg13g2_a21o_1 11
sg13g2_a21oi_1 336
sg13g2_a21oi_2 6
sg13g2_a221oi_1 10
sg13g2_a22oi_1 70
Number of cells: 3137
sg13g2_a21o_1 29
sg13g2_a21oi_1 379
sg13g2_a21oi_2 3
sg13g2_a221oi_1 15
sg13g2_a22oi_1 76
sg13g2_and2_1 3
sg13g2_and3_1 3
sg13g2_buf_1 66
sg13g2_buf_16 3
sg13g2_buf_2 107
sg13g2_buf_4 78
sg13g2_buf_8 32
sg13g2_and3_1 5
sg13g2_and4_1 1
sg13g2_buf_1 88
sg13g2_buf_2 104
sg13g2_buf_4 54
sg13g2_buf_8 24
sg13g2_dfrbp_1 78
sg13g2_inv_1 173
sg13g2_inv_2 18
sg13g2_inv_1 215
sg13g2_inv_2 19
sg13g2_inv_4 4
sg13g2_mux2_1 1
sg13g2_nand2_1 951
sg13g2_nand2_2 52
sg13g2_nand2b_1 22
sg13g2_nand2b_2 1
sg13g2_nand3_1 251
sg13g2_nand3b_1 20
sg13g2_nand4_1 10
sg13g2_nor2_1 439
sg13g2_nor2_2 47
sg13g2_nor2b_1 34
sg13g2_nor2b_2 3
sg13g2_nor3_1 84
sg13g2_nor3_2 1
sg13g2_nor4_1 16
sg13g2_nor4_2 1
sg13g2_o21ai_1 166
sg13g2_or2_1 1
sg13g2_or3_1 1
sg13g2_nand2_1 806
sg13g2_nand2_2 44
sg13g2_nand2b_1 41
sg13g2_nand3_1 263
sg13g2_nand3b_1 14
sg13g2_nand4_1 21
sg13g2_nor2_1 405
sg13g2_nor2_2 40
sg13g2_nor2b_1 28
sg13g2_nor2b_2 4
sg13g2_nor3_1 109
sg13g2_nor3_2 3
sg13g2_nor4_1 9
sg13g2_o21ai_1 238
sg13g2_or2_1 2
sg13g2_tiehi 1
sg13g2_tielo 1
sg13g2_xnor2_1 27
sg13g2_xnor2_1 8
sg13g2_xor2_1 3

Chip area for module '\tt_um_phansel_laplace_lut': 29849.677200
of which used for sequential elements: 3679.603200 (12.33%)
Chip area for module '\tt_um_phansel_laplace_lut': 29620.836000
of which used for sequential elements: 3679.603200 (12.42%)

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