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i wish to do a formal verification (logic equalence checks etc) for my designs.
i recently came to know about the yosys's sby and eqy tools,
but is there any move towards this in openlane's yosys regarding mentioned above?
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i wish to do a formal verification (logic equalence checks etc) for my designs.
i recently came to know about the yosys's sby and eqy tools,
but is there any move towards this in openlane's yosys regarding mentioned above?
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