Dockerized Openlane - yosis systemverilog support

[Andrea-Spitale]

Hello,
I am using Openlane through the docker image, as recommended. I'd like to have a way to write down code in systemverilog and have the flow correctly read and synthesize it. I know it is possible if using either sv2v or surelog+uhdm. I was trying to install the yosis-systemverilog plugin that antmicro hosts at https://github.com/antmicro/yosys-systemverilog, but I get an error like the one reported in the issue link below

chipsalliance/synlig#1776

I tried to update glibc from 2.17 to 2.29+, but I understood I need to modify the docker image dependencies and rebuild the docker image, am I right? If so, what's the proper way to do it? I tried to follow the developer guide on customizing the docker image, but I have some issues with it, such that the process fails to complete the "build-build-base"

According to your experience, what would be as of today the best approach, relying on sv2v or use surelog?

Thanks!

[Andrea-Spitale]

I think the best approach if one wants the way some tools work (assuming this can't be achieved by changing the open lane scripts) is to install openlane or open road locally. I have also reported the issue to the Yosys-systemverilog plugin team and they are working on getting rid of the Libc dependency. When that will be done, then I believe one will be able to use the dockerized image of openlane and load the yosys sytemverilog plugin without any issue.