config.json

{
    "//": "Basics",
    "DESIGN_NAME": "spm",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_PERIOD": 10,
    "CLOCK_PORT": "clk",
    "PNR_SDC_FILE": "dir::src/spm.sdc",
    "SIGNOFF_SDC_FILE": "dir::src/spm.sdc",
    "//": "PDN",
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "FP_PDN_VWIDTH": 2,
    "FP_PDN_HWIDTH": 2,
    "FP_PDN_VPITCH": 30,
    "FP_PDN_HPITCH": 30,
    "FP_PDN_SKIPTRIM": true,
    "//": "Pin Order",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "//": "Technology-Specific Configs",
    "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "CLOCK_PERIOD": 10,
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "MAX_FANOUT_CONSTRAINT": 5
        }
    },
    "pdk::gf180mcu*": {
        "CLOCK_PERIOD": 24.0,
        "FP_CORE_UTIL": 40,
        "MAX_FANOUT_CONSTRAINT": 4,
        "PL_TARGET_DENSITY": 0.5
    }
}