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Merge pull request #81 from SW-CSA/cel_develop
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Change the min threshold of power chip
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MickeyZhan authored Jul 17, 2019
2 parents 9f54a66 + 11fb625 commit 2e8e360
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Showing 2 changed files with 5 additions and 5 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -31,14 +31,14 @@ board_type=$(board_type)
#IR38060
set_value 4 43 in0_min 950
set_value 4 43 in0_max 1100
set_value 4 43 curr1_min 0
set_value 4 43 curr1_min -100
set_value 4 43 curr1_max 6000
set_value 4 43 in0_label "Basebord_FPGA_1.0V Voltage"
set_value 4 43 curr1_label "Basebord_FPGA_1.0V Current"

set_value 17 47 in0_min 1160
set_value 17 47 in0_max 1240
set_value 17 47 curr1_min 0
set_value 17 47 curr1_min -100
set_value 17 47 curr1_max 6000
set_value 17 47 in0_label "SWITCH_Analog/Digital_1.2V Voltage"
set_value 17 47 curr1_label "SWITCH_Analog/Digital_1.2V Current"
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Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ set_value 17 45 in0_max 1050
set_value 17 45 in0_min 950
set_value 17 45 curr1_label "Switch_FPGA_1.0V Current"
set_value 17 45 curr1_max 1500
set_value 17 45 curr1_min 0
set_value 17 45 curr1_min -100
set_value 17 49 in0_label "Switch_PVDD_0.8V Voltage"
set_value 17 49 in0_max 880
set_value 17 49 in0_min 760
Expand Down Expand Up @@ -136,7 +136,7 @@ set_value 20 45 in0_max 1890
set_value 20 45 in0_min 1710
set_value 20 45 curr1_label "TOP_LC_VDDIO_1.8V Current"
set_value 20 45 curr1_max 2000
set_value 20 45 curr1_min 0
set_value 20 45 curr1_min -100
set_value 21 30 in0_label "BOTTOM_LC_port&CPLD_Supply_3.3V Voltage"
set_value 21 30 in0_max 1732
set_value 21 30 in0_min 1568
Expand Down Expand Up @@ -172,7 +172,7 @@ set_value 22 45 in0_max 1890
set_value 22 45 in0_min 1710
set_value 22 45 curr1_label "BOTTOM_LC_VDDIO_1.8V Current"
set_value 22 45 curr1_max 2000
set_value 22 45 curr1_min 0
set_value 22 45 curr1_min -100
set_value 23 45 in0_label "Switch_Standby_3.3V Voltage"
set_value 23 45 in0_max 3465
set_value 23 45 in0_min 3135
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