This repository has been archived by the owner on Mar 24, 2021. It is now read-only.
Verilator testbench for ISA tests #8
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Changed FPGA build makefile to use e203 as a default CORE and did few minor enhancements. Updated SDK makefile to let users re-define toolchain binaries names from environment. This shall help using different pre-compiled toolchains.
Testbench and Makefile added into a separate folder (originating from the existing ISA tests testbench). Minor updates to Verilog code to let it work with Verilator. Run with v3.924 and --trace enabled (without --trace the simulation does not converge/end).
Also added help target to the Makefile so that it becomes the default one. Added README file with instructions and known limitations. Added license statements (Apache 2.0).
Sign up for free
to subscribe to this conversation on GitHub.
Already have an account?
Sign in.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This pull requests adds a testbench and Makefile to run ISA tests against RTL with Verilator.
There are minor changes in RTL to make it work with Verilator. Minor changes also made in fpga and SDK Makefiles (these are not needed for the Verilator testbech).