Junior Researcher. Scope of activity: EDA, P&R, STA, SI
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04:07
(UTC +03:00) - in/rustam-chochaev-a37057240
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circuit_training_openlane
circuit_training_openlane PublicInstructions on how to run Circuit Training in OpenLane flow
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MacroPlacement
MacroPlacement PublicForked from TILOS-AI-Institute/MacroPlacement
*** README ***: for convertors checkout this branch: pb2def
Verilog 1
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OpenLane
OpenLane PublicForked from The-OpenROAD-Project/OpenLane
** README **: OpenLane+DREAMPlace (PL_DREAMPLACE_GLB_PLACEMENT in config.json) option for global placement in fpi branch
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transistor_counter
transistor_counter PublicSimple transistor counter in Verilog gate-level netlist using data from CDL
Rust 1
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