nrfx 3.6.0 release

Signed-off-by: Nikodem Kastelik <[email protected]>

CHANGELOG.md

@@ -1,6 +1,27 @@
 # Changelog
 All notable changes to this project are documented in this file.
 
+## [3.6.0] - 2024-07-26
+### Added
+- Added support for nRF54L20 Eng A and nRF9230 Eng B.
+- Added support for enabling and disabling the SPIM peripheral instance for nRF54H20 outside of driver context in the SPIM driver.
+- Added support for FRAMETIMEOUT event in the UARTE HAL.
+- Added support for SOFTRESET task in the RADIO HAL.
+- Added optimized functions for reading inputs, writing outputs and configuring direction of GPIO ports in the GPIO HAL.
+- Added getters for BLE address, BLE IR, and BLE ER in the FICR HAL.
+- Implemented a workaround for the anomaly 89 on the nRF52832 SoC in the TWIM and SPIM HALs.
+
+### Changed
+- Updated MDK to version 8.66.0.
+- Removed unsupported GPIO pin drive settings from the GPIO HAL.
+
+### Fixed
+- Fixed spurious assertion in the TIMER driver. Now, the nrfx_timer_extended_compare() function can be called after the TIMER has started.
+- Fixed potential data corruption when cache bounce buffer and RX FIFO buffer were shared in the UARTE driver.
+- Fixed handling of events having respective interrupts disabled in the UARTE driver.
+- Fixed dropping of data in case of RX abort in the UARTE driver.
+- Fixed frequency symbol setting in case of non-secure build on the nRF54L15 SoC.
+
 ## [3.5.0] - 2024-05-10
 ### Added
 - Added function for freeing all allocated channels in the WDT driver.

doc/nrf54l15_enga.dox

@@ -1,5 +1,5 @@
 /**
-@page nrf54l15_enga_drivers nRF54L15 EngA drivers
+@page nrf54l15_enga_drivers nRF54L15 Eng A drivers
 
 This page lists nrfx driver components supported by the nRF54L15 EngA SoC.
 For a complete overview, see @ref nrfx_drv_supp_matrix.

doc/nrf54l20_enga.dox

@@ -0,0 +1,84 @@
+/**
+@page nrf54l20_enga_drivers nRF54L20 Eng A drivers
+
+This page lists nrfx driver components supported by the nRF54L20 EngA SoC.
+For a complete overview, see @ref nrfx_drv_supp_matrix.
+
+@{
+
+@ref nrf_aar
+
+@ref nrf_cache
+
+@ref nrf_ccm
+
+@ref nrf_clock
+
+@ref nrf_comp
+
+@ref nrf_cracen
+
+@ref nrf_systick
+
+@ref nrf_dppi
+
+@ref nrf_egu
+
+@ref nrf_glitchdet
+
+@ref nrf_gpio
+
+@ref nrf_gpiote
+
+@ref nrf_grtc
+
+@ref nrf_icr
+
+@ref nrf_kmu
+
+@ref nrf_lpcomp
+
+@ref nrf_memconf
+
+@ref nrf_mpc
+
+@ref nrf_nfct
+
+@ref nrf_power
+
+@ref nrf_ppib
+
+@ref nrf_pwm
+
+@ref nrf_qdec
+
+@ref nrf_radio
+
+@ref nrf_rramc
+
+@ref nrf_saadc
+
+@ref nrf_spim
+
+@ref nrf_spis
+
+@ref nrf_spu
+
+@ref nrf_tampc
+
+@ref nrf_temp
+
+@ref nrf_timer
+
+@ref nrf_twim
+
+@ref nrf_twis
+
+@ref nrf_uarte
+
+@ref nrf_vpr
+
+@ref nrf_wdt
+
+@}
+*/

doc/nrf9230_engb.dox

@@ -0,0 +1,100 @@
+/**
+@page nrf9230_engb_drivers nRF9230 Eng B drivers
+
+This page lists nrfx driver components supported by the nRF9230 EngB SoC.
+For a complete overview, see @ref nrfx_drv_supp_matrix.
+
+@{
+
+@ref nrf_aar
+
+@ref nrf_auxpll
+
+@ref nrf_bellboard
+
+@ref nrf_cache
+
+@ref nrf_ccm
+
+@ref nrf_comp
+
+@ref nrf_systick
+
+@ref nrf_ctrlap
+
+@ref nrf_dppi
+
+@ref nrf_egu
+
+@ref nrf_exmif
+
+@ref nrf_icr
+
+@ref nrf_gpio
+
+@ref nrf_gpiote
+
+@ref nrf_grtc
+
+@ref nrf_ipct
+
+@ref nrf_lpcomp
+
+@ref nrf_lrc
+
+@ref nrf_memconf
+
+@ref nrf_mpc
+
+@ref nrf_mutex
+
+@ref nrf_mvdma
+
+@ref nrf_nfct
+
+@ref nrf_pdm
+
+@ref nrf_ppib
+
+@ref nrf_pwm
+
+@ref nrf_qdec
+
+@ref nrf_radio
+
+@ref nrf_ramc
+
+@ref nrf_resetinfo
+
+@ref nrf_saadc
+
+@ref nrf_spim
+
+@ref nrf_spis
+
+@ref nrf_spu
+
+@ref nrf_stm
+
+@ref nrf_tampc
+
+@ref nrf_tbm
+
+@ref nrf_tdm
+
+@ref nrf_timer
+
+@ref nrf_twim
+
+@ref nrf_twis
+
+@ref nrf_uarte
+
+@ref nrf_usbhs
+
+@ref nrf_vpr
+
+@ref nrf_wdt
+
+@}
+*/

doc/nrfx.doxyfile

@@ -50,7 +50,7 @@ PROJECT_NAME           = "nrfx"
 
 ### EDIT THIS ###
 
-PROJECT_NUMBER         = "3.5"
+PROJECT_NUMBER         = "3.6"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a

doc/sphinx/drv_supp_matrix.rst

@@ -14,7 +14,9 @@ Driver support overview
    nrf5340
    nrf54h20
    nrf54l15_enga
+   nrf54l20_enga
    nrf91_series
+   nrf9230_engb
 
 .. role:: red
 .. role:: green

doc/sphinx/nrf54l15_enga.rst

@@ -1,5 +1,5 @@
-nRF54L15 EngA drivers
-=====================
+nRF54L15 Eng A drivers
+======================
 
 .. doxygenpage:: nrf54l15_enga_drivers
     :content-only:

doc/sphinx/nrf54l20_enga.rst

@@ -0,0 +1,5 @@
+nRF54L20 Eng A drivers
+======================
+
+.. doxygenpage:: nrf54l20_enga_drivers
+    :content-only:

doc/sphinx/nrf9230_engb.rst

@@ -0,0 +1,5 @@
+nRF9230 Eng B drivers
+=====================
+
+.. doxygenpage:: nrf9230_engb_drivers
+    :content-only:

drivers/include/nrfx_spim.h

@@ -160,10 +160,10 @@ typedef struct
     .mode           = NRF_SPIM_MODE_0,                                                           \
     .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,                                              \
     .miso_pull      = NRF_GPIO_PIN_NOPULL,                                                       \
+    NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.dcx_pin = NRF_SPIM_PIN_NOT_CONNECTED,), ())   \
+    NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.rx_delay = NRF_SPIM_RXDELAY_DEFAULT,), ())    \
     NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.use_hw_ss = false,), ())                      \
     NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.ss_duration = NRF_SPIM_CSNDUR_DEFAULT,), ())  \
-    NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.rx_delay = NRF_SPIM_RXDELAY_DEFAULT,), ())    \
-    NRFX_COND_CODE_1(NRFX_SPIM_EXTENDED_ENABLED, (.dcx_pin = NRF_SPIM_PIN_NOT_CONNECTED,), ())   \
 }
 
 /**

drivers/include/nrfx_uarte.h

@@ -601,6 +601,7 @@ nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
  *
  * @retval NRFX_SUCCESS         The receiving operation is completed.
  * @retval NRFX_ERROR_BUSY      The receiver did not complete the operation.
+ * @retval NRFX_ERROR_ALREADY   The receiver is disabled.
  * @retval NRFX_ERROR_FORBIDDEN Operation is not supporting in the current configuration.
  */
 nrfx_err_t nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance, size_t * p_rx_amount);

drivers/src/nrfx_gpiote.c

@@ -825,7 +825,7 @@ static nrfx_err_t gpiote_init(nrfx_gpiote_t const * p_instance, uint8_t interrup
     nrfy_gpiote_int_init(p_instance->p_reg,
                          (uint32_t)NRF_GPIOTE_INT_PORT_MASK,
                          interrupt_priority,
-                         true,
+                         false,
                          p_cb->channels_number);
 
     p_cb->state = NRFX_DRV_STATE_INITIALIZED;
@@ -1017,6 +1017,11 @@ static void pin_trigger_enable(nrfx_gpiote_t const * p_instance,
 {
     NRFX_ASSERT(pin_has_trigger(p_instance, pin));
 
+    if (!nrfy_gpiote_int_enable_check(p_instance->p_reg, (uint32_t)NRF_GPIOTE_INT_PORT_MASK))
+    {
+        nrfy_gpiote_int_enable(p_instance->p_reg, (uint32_t)NRF_GPIOTE_INT_PORT_MASK);
+    }
+
     if (pin_in_use_by_te(p_instance, pin) && pin_is_input(p_instance, pin))
     {
         uint8_t ch = pin_te_get(p_instance, pin);

drivers/src/nrfx_grtc.c

@@ -855,7 +855,7 @@ nrfx_err_t nrfx_grtc_syscounter_cc_int_enable(uint8_t channel)
         return err_code;
     }
     channel_used_mark(channel);
-    nrfy_grtc_sys_counter_compare_event_int_clear_enable(NRF_GRTC, channel, true);
+    nrfy_grtc_int_enable(NRF_GRTC, GRTC_CHANNEL_TO_BITMASK(channel));
     NRFX_LOG_INFO("GRTC SYSCOUNTER compare interrupt for channel %u enabled.", (uint32_t)channel);
     return err_code;
 }

drivers/src/nrfx_spim.c

@@ -154,8 +154,9 @@ typedef struct
     nrfx_spim_evt_t         evt;  // Keep the struct that is ready for event handler. Less memcpy.
     nrfx_drv_state_t        state;
     volatile bool           transfer_in_progress;
-    bool                    skip_gpio_cfg  : 1;
-    bool                    ss_active_high;
+    bool                    skip_gpio_cfg       : 1;
+    bool                    ss_active_high      : 1;
+    bool                    disable_on_xfer_end : 1;
     uint32_t                ss_pin;
 } spim_control_block_t;
 static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT];
@@ -212,7 +213,12 @@ static void spim_abort(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb)
         NRFX_LOG_ERROR("Failed to stop instance with base address: %p.", (void *)p_spim);
     }
     p_cb->transfer_in_progress = false;
-    nrfy_spim_disable(p_spim);
+#if defined(HALTIUM_XXAA)
+    if (p_cb->disable_on_xfer_end)
+#endif
+    {
+        nrfy_spim_disable(p_spim);
+    }
 }
 
 static void pin_init(uint32_t             pin,
@@ -802,6 +808,12 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type               * p_spim,
     nrfy_spim_buffers_set(p_spim, &xfer_desc);
 
     nrfy_spim_event_clear(p_spim, NRF_SPIM_EVENT_END);
+#if defined(HALTIUM_XXAA)
+    p_cb->disable_on_xfer_end = (flags & (NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER |
+                                          NRFX_SPIM_FLAG_HOLD_XFER |
+                                          NRFX_SPIM_FLAG_REPEATED_XFER)) ?
+                                true : !nrfy_spim_enable_check(p_spim);
+#endif
     nrfy_spim_enable(p_spim);
 
     if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))

drivers/src/nrfx_timer.c

@@ -317,7 +317,7 @@ void nrfx_timer_extended_compare(nrfx_timer_t const *   p_instance,
                                  nrf_timer_short_mask_t timer_short_mask,
                                  bool                   enable_int)
 {
-    NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED);
+    NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
 
     nrfy_timer_shorts_disable(p_instance->p_reg,
         (uint32_t)(NRF_TIMER_SHORT_COMPARE0_STOP_MASK  << cc_channel) |